公开(公告)号：US07015637B2

公开(公告)日：2006-03-21

申请号：US10637624

申请日：2003-08-11

Applicant: Yoshimi Uda ,  Kazuya Ishiwata ,  Shinsaku Kubo ,  Yasuyuki Watanabe

Inventor： Yoshimi Uda ,  Kazuya Ishiwata ,  Shinsaku Kubo ,  Yasuyuki Watanabe

IPC: H01J19/66 ,  H01J19/82

CPC classification number: H05K1/0271 ,  H01J29/02 ,  H01J31/127 ,  H01J2329/0489 ,  H01J2329/861 ,  H05K1/092 ,  H05K3/248 ,  H05K2201/035 ,  H05K2201/09745 ,  H05K2203/0514 ,  Y10T29/49147 ,  Y10T29/49174 ,  Y10T29/53204 ,  Y10T29/53209

Abstract: As a substrate having a fine line and capable of suppressing crack generation in the substrate and peeling of the fine line, the invention discloses a configuration in which plural recesses are arranged on the fine line, and particularly a configuration in which the interval of the plural recesses does not exceed 200 μm. There is also disclosed a configuration in which the plural recesses are arranged along a direction crossing the longitudinal direction of the fine line.

公开(公告)号：US6097246A

公开(公告)日：2000-08-01

申请号：US069164

申请日：1998-04-29

Applicant: Kazuyuki Tsurunaga ,  Jun Matsuzaki ,  Hiroshi Ohashi ,  Hideki Hachiya

Inventor： Kazuyuki Tsurunaga ,  Jun Matsuzaki ,  Hiroshi Ohashi ,  Hideki Hachiya

IPC: H01H33/28 ,  H01H33/66 ,  H02H3/02 ,  H01J19/82

CPC classification number: H01H33/285 ,  H02H3/025 ,  H01H33/66

Abstract: The present invention includes a first switch 4a, a second switch 4b and a capacitor 4d. The first switch 4a normally in a closed state is connected in series between a power source 1 and load, and opens when an accident builds up. The second switch 4b normally in an open state closes almost simultaneously with the opening of the first switch 4a. The capacity 4d normally charged by an arbitrary voltage has predetermined electrically capacity. The serial connected circuit consists of the second switch 4b and capacitor 4d, it is connected in parallel to the first switch 4a.

Abstract translation: 本发明包括第一开关4a，第二开关4b和电容器4d。 通常处于关闭状态的第一开关4a串联连接在电源1和负载之间，并在事故发生时打开。 通常处于打开状态的第二开关4b几乎与第一开关4a的开启同时闭合。 通常由任意电压充电的容量4d具有预定的电容。 串联电路由第二开关4b和电容器4d组成，并联连接到第一开关4a。

公开(公告)号：US6081150A

公开(公告)日：2000-06-27

申请号：US55766

申请日：1998-04-07

Applicant: Tomoya Yamaura ,  Nobuhiko Watanabe

Inventor： Tomoya Yamaura ,  Nobuhiko Watanabe

IPC: H03G3/02 ,  H03G1/00 ,  H01J19/82

CPC classification number: H03G1/0088

Abstract: In a control voltage producing apparatus, either a pulse-duration modulation signal or a pulse-width modulation signal, which are generated in response to a digital control signal, is from a first buffer circuit to an averaging circuit so as to be averaged. A power supply voltage is supplied from a first voltage source to this first buffer circuit. Then, the averaged signal is supplied to a control voltage producing circuit for producing a target control voltage. When a control voltage is produced, the same output voltage as that of the first buffer circuit is generated by a second buffer circuit, and then is supplied to the control voltage generating circuit and an operation control circuit. In response to the output voltage derived from the second buffer circuit, the operation control circuit applies the power supply voltage to the control voltage producing circuit so as to cause this control voltage producing circuit to be operable. Also, the control voltage producing circuit uses the output voltage derived from the second buffer circuit as the reference voltage so as to regulate the control voltage. As a consequence, in response to one of the output voltages derived from the second buffer circuit, turning ON/OFF of the control voltage producing circuit can be controlled, and further the reference voltage used to regulate the control voltage can be applied.

Abstract translation: 在控制电压产生装置中，响应于数字控制信号而产生的脉冲持续时间调制信号或脉冲宽度调制信号从第一缓冲电路到平均电路被平均化。 电源电压从第一电压源提供给该第一缓冲电路。 然后，平均信号被提供给用于产生目标控制电压的控制电压产生电路。 当产生控制电压时，通过第二缓冲电路产生与第一缓冲电路相同的输出电压，然后提供给控制电压产生电路和操作控制电路。 响应于从第二缓冲电路导出的输出电压，操作控制电路将电源电压施加到控制电压产生电路，以使该控制电压产生电路可操作。 此外，控制电压产生电路使用从第二缓冲电路导出的输出电压作为参考电压，以便调节控制电压。 结果，响应于从第二缓冲电路导出的一个输出电压，可以控制控制电压产生电路的接通/断开，并且还可以应用用于调节控制电压的参考电压。

公开(公告)号：US5812014A

公开(公告)日：1998-09-22

申请号：US726282

申请日：1996-10-04

Applicant: Michelangelo Mazzucco ,  Giampietro Maggioni

Inventor： Michelangelo Mazzucco ,  Giampietro Maggioni

IPC: H02M7/217 ,  H01J19/82

CPC classification number: H02M7/217

Abstract: A double half-wave rectifier circuit with earth shift using an input differential amplifier and two current mirrors in cascode configuration in such a way that the input current is transferred to the output via one or the other of the current mirrors depending on whether the input signal voltage is greater than or less than an input reference voltage and therefore the current is positive or negative.

Abstract translation: 具有接地移位的双半波整流电路，其使用输入差分放大器和两个共模共栅配置的电流镜，使得根据输入信号是否经由一个或另一个电流镜将输入电流传输到输出端 电压大于或小于输入参考电压，因此电流为正或负。

公开(公告)号：US5783965A

公开(公告)日：1998-07-21

申请号：US663904

申请日：1996-06-14

Applicant: Hajime Iwatsuki ,  Hideo Sugawara

Inventor： Hajime Iwatsuki ,  Hideo Sugawara

IPC: H03F3/60 ,  H03F1/34 ,  H03F1/56 ,  H03F3/191 ,  H01J19/82

CPC classification number: H03F1/30 ,  H03F1/56 ,  H03F3/191 ,  H03F2200/372

Abstract: A transistor bias circuit which achieves stable operation in a multistage-connected amplifier circuit or in a compound circuit is formed, for example, by a transistor amplifier and a mixer. The transistor bias circuit, which establishes the operating point of a transistor, has an input biasing circuit which is connected to a signal input terminal of the transistor and which applies a bias current to this input terminal from a power supply. The input biasing circuit has an input frequency selection unit which passes an AC input signal input to the transistor signals input terminal within a prescribed frequency band, and which attenuates an AC input signal input to the transistor signal input terminal outside the prescribed frequency band.

Abstract translation: 例如通过晶体管放大器和混频器形成在多级连接放大器电路或复合电路中实现稳定工作的晶体管偏置电路。 建立晶体管的工作点的晶体管偏置电路具有输入偏置电路，该输入偏置电路连接到晶体管的信号输入端并从电源向该输入端施加偏置电流。 输入偏置电路具有输入频率选择单元，该输入频率选择单元将输入到晶体管信号输入端的AC输入信号传递到规定频带内，并且将在输入到晶体管信号输入端子的规定频带外的AC输入信号衰减。

公开(公告)号：US5543748A

公开(公告)日：1996-08-06

申请号：US413766

申请日：1995-03-30

Applicant: Yuji Ando

Inventor： Yuji Ando

IPC: H03K3/315 ,  H03K3/36 ,  H01J19/82

CPC classification number: B82Y10/00 ,  H03K3/36

Abstract: A flip-flop circuit which makes use of a resonant-tunneling effect is improved in that it is simplified in structure and hence in designing of a component and operates at a room temperature. The flip-flop circuit includes a bipolar transistor and a resonant-tunneling diode. The collector terminal of the bipolar transistor is connected to a voltage source, and the base terminal is connected to an input terminal of the flip-flop circuit by way of a resistor. One of a pair of terminals of the resonant-tunneling diode is grounded while the other terminal is connected to the emitter terminal of the bipolar transistor with a junction therebetween connected to an output terminal of the flip-flop circuit. The bipolar transistor is set such that, when the value of a current flowing into the base terminal has a high level, the value of a current flowing through the collector terminal is higher than a peak current value of the resonant-tunneling diode, but when the value of the current flowing into the base terminal has a low level, the value of the current flowing through the collector terminal is lower than a valley current value of the resonant-tunneling diode.

Abstract translation: 利用谐振隧道效应的触发器电路得到改进，其结构简单，因此在部件的设计中被简化并在室温下工作。 触发器电路包括双极晶体管和谐振隧道二极管。 双极晶体管的集电极连接到电压源，基极通过电阻连接到触发器电路的输入端。 谐振隧道二极管的一对端子中的一个接地，而另一个端子连接到双极晶体管的发射极端子，其两端连接到触发器电路的输出端子。 双极型晶体管的设定使得当流入基极的电流值为高电平时，流过集电极端子的电流值高于谐振隧道二极管的峰值电流值，但是当 流入基极的电流值为低电平，流过集电极端子的电流值低于谐振隧道二极管的谷值电流值。

公开(公告)号：US5530394A

公开(公告)日：1996-06-25

申请号：US318355

申请日：1994-10-05

Applicant: Lothar Blossfeld ,  Ulrich Theus ,  Mario Motz

Inventor： Lothar Blossfeld ,  Ulrich Theus ,  Mario Motz

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K17/0814 ,  H03K17/10 ,  H01J19/82 ,  G05F1/10 ,  G05F3/16 ,  H03K3/59

CPC classification number: H03K17/102 ,  H01L27/0266 ,  H01L27/092 ,  H03K17/08142 ,  H01L2924/0002

Abstract: In a CMOS circuit having at least a first subcircuit coupled between a first point of potential and a first circuit node, and having a second subcircuit coupled between a second circuit node and a second point of potential, said first and second circuit nodes being coupled together, the improvement in combination therewith, comprising: first circuit means coupled to the first point of potential for converting the first potential to a third potential as a function of the magnitude of said first potential, said third potential being of a value inbetween the first and second potentials; a FET having source, drain, gate and well terminals, said source terminal being coupled to said well terminal and to said first circuit node, said third potential being applied to said gate terminal, said drain terminal being coupled to said second circuit node; wherein said FET, in conjunction with said first circuit means, operates to selectively provide a difference in potential between said first and second circuit nodes, thereby preventing voltage breakdown within said subcircuits.

Abstract translation: 在具有耦合在第一电位点和第一电路节点之间的至少第一子电路并且具有耦合在第二电路节点和第二电位点之间的第二子电路的CMOS电路中，所述第一和第二电路节点耦合在一起 与其组合的改进包括：耦合到第一电位点的第一电路装置，用于将第一电位转换为第三电位，作为所述第一电位的大小的函数，所述第三电位在第一和第 第二个潜力; 具有源极，漏极，栅极和阱端子的FET，所述源极端子耦合到所述阱极端子和所述第一电路节点，所述第三电位被施加到所述栅极端子，所述漏极端子耦合到所述第二电路节点; 其中所述FET结合所述第一电路装置操作以选择性地提供所述第一和第二电路节点之间的电位差，由此防止所述子电路内的电压击穿。

公开(公告)号：US4594554A

公开(公告)日：1986-06-10

申请号：US509517

申请日：1983-06-30

Applicant: Jerome D. Schick

Inventor： Jerome D. Schick

IPC: H01J37/06 ,  H01J1/13 ,  H01J37/24 ,  H01J37/244 ,  H01J19/82 ,  H05G1/52

CPC classification number: H01J37/242 ,  H01J1/135

Abstract: A method of extending the lifetime of an electron beam filament, typically LaB.sub.6 by applying power to the filament over a preselected period in a substantially linear manner. The time period is typically 20 minutes before a steady state power level is attained with a fully stabilized instrument. Power-down is a reverse of the power-up sequence until all power is removed.

Abstract translation: 一种延长电子束灯丝寿命的方法，通常在大部分线性方式的预选时间内，通过在灯丝上施加电力来延长寿命。 在完全稳定的仪器达到稳态功率水平之前，时间通常为20分钟。 断电功能与上电顺序相反，直到所有电源都被去除。

公开(公告)号：US4245176A

公开(公告)日：1981-01-13

申请号：US936372

申请日：1978-08-24

Applicant: Russell E. Anglin

Inventor： Russell E. Anglin

IPC: H01J29/98 ,  H04N5/63 ,  H01J19/82

CPC classification number: H04N5/63 ,  H01J29/98

Abstract: A voltage multiplier device is disclosed which includes a circuit and a means for coupling the circuit between a television filament transformer and the heater filament leads of a C.R.T. picture tube of a television set. The device is operative to develop a voltage across the two leads of the C.R.T. heater filament that is greater than the voltage developed across the two secondary leads of the transformer.

Abstract translation: 公开了一种电压倍增器装置，其包括电路和用于耦合电视灯丝变压器和C.R.T.的加热器灯丝引线之间的电路的装置。 电视机的显像管。 该装置用于在C.R.T的两个引线上产生电压。 加热器灯丝大于在变压器的两个次级引线上产生的电压。

公开(公告)号：US3805174A

公开(公告)日：1974-04-16

申请号：US30875972

申请日：1972-11-22

Applicant: ITT

Inventor： SCHLATTER G

IPC: G01N9/00 ,  H01J19/82

CPC classification number: G01N9/002 ,  G01N2009/008

Abstract: An alternating signal is transformer coupled to an input circuit with rectification to provide an isolated source of potential without the use of a power supply.

Abstract translation: 交流信号被变换器耦合到具有整流的输入电路，以在不使用电源的情况下提供隔离的电位。