公开(公告)号：US10255847B2

公开(公告)日：2019-04-09

申请号：US15916605

申请日：2018-03-09

申请人： LAPIS Semiconductor Co., Ltd.

发明人： Hiroshi Tsuchi

IPC分类号： G06F3/038 ,  G09G5/00 ,  G09G3/20 ,  G11C19/00 ,  H03K19/017 ,  H03K19/0185

摘要： A level shift circuit is configured to receive reference voltage and first to third voltages, and to generate an output signal. The voltages satisfy a condition in which the reference voltage the first voltage>the second voltage>the third voltage. The level shift circuit includes a first level shift circuit configured to receive a first signal having a first amplitude within a difference between the reference and first voltages, and level shift the first signal to a second signal having a second amplitude within a difference between the reference and second voltages, and a second level shift circuit configured to level shift the second signal to a third signal having a third amplitude within a difference between the reference and third voltages, and output the third signal as the output signal.

公开(公告)号：US10250260B2

公开(公告)日：2019-04-02

申请号：US15811057

申请日：2017-11-13

申请人： SEIKO EPSON CORPORATION

发明人： Ryuichi Kagaya

IPC分类号： H03K19/013 ,  H03K17/16 ,  H03K19/017

摘要： A data communication system has a first data communication circuit for outputting a clock signal to a clock signal line, receiving data input from a data signal line, and outputting data as open drain output to the data signal line, a second data communication circuit for receiving input of a clock signal from the clock signal line, receiving input of data from the data signal line, and outputting data as open drain output to the data signal line, a first pull-up resistor connected between the data signal line and the wiring of a power supply potential, a second pull-up resistor for selectively pulling up the data signal line, and a pull-up control circuit that is connected to the second pull-up resistor, and strengthens pull-up of the data signal line at least in response to a clock signal.

公开(公告)号：US10224930B2

公开(公告)日：2019-03-05

申请号：US15964245

申请日：2018-04-27

申请人： dSPACE digital signal processing and control engineering GmbH

发明人： Dominik Lubeley ,  Marc Schlenger ,  Heiko Kalte

IPC分类号： H03K19/003 ,  H03K19/017 ,  G01R31/317 ,  H03K19/0175

摘要： A method for detecting the topology of electrical wiring between at least two field-programmable gate arrays (FPGAs) includes implementing a first receive register on a second interface pin; implementing a first send register on a first driver; activating the first driver via a first activation signal; emitting, by the first driver, a first signal, wherein the first signal is defined by the first send register; reading out, by a first receive register, whether the first signal is received at the second interface pin; and allocating the second interface pin to the first interface pin if the first signal from the first driver is received at the second interface pin.

公开(公告)号：US20190041452A1

公开(公告)日：2019-02-07

申请号：US15670855

申请日：2017-08-07

申请人： Google LLC

发明人： Chiu-Mao Chang ,  Chih-Chung Chang

IPC分类号： G01R31/28 ,  H03K19/017

摘要： Techniques are disclosed for increasing a quantity of candidate electronic-component states determinable from one or more input pins. The techniques may use an internal pull resistor to test a strength of an external resistor to gain two extra candidate pin states. Additional candidate electronic-component states are then gained based on the extra candidate pin states, combinations of pin states of two or more input pins, and/or detecting a short between two or more input pins.

公开(公告)号：US10128904B2

公开(公告)日：2018-11-13

申请号：US14748079

申请日：2015-06-23

申请人： NVIDIA Corporation

发明人： William J. Dally

IPC分类号： H04B3/36 ,  H03K19/017 ,  H04L25/02 ,  H04B1/56

摘要： A repeater circuit is disclosed. The repeater circuit is coupled to a transmission line driven by a first transmitter circuit and configured to detect a signal transition from a first voltage level to a second voltage level at a first position on the transmission line. The repeater circuit then reinforces the signal transition from the second voltage level to a third voltage level at the first position on the transmission line without interrupting a current through the transmission line.

公开(公告)号：US20180287611A1

公开(公告)日：2018-10-04

申请号：US15768549

申请日：2016-10-24

申请人： Ari PAASIO

发明人： Ari PAASIO

IPC分类号： H03K19/00 ,  H03K19/017 ,  H03K19/0944

CPC分类号： H03K19/0013 ,  G05F3/20 ,  H03K19/0027 ,  H03K19/01707 ,  H03K19/09441

摘要： According to the invention, only one type of enhancement MOS transistor type is used in implementing typical Boolean functions in hardware. Preferably, the MOS transistor type allows back bias control for adjusting and compensating the operation conditions. When implemented in PMOS only transistors, the pull-down functionality is performed by a single transistor with its gate and source connected to the output, This type of connection ensures that the pull-down functionality is performed by the leakage current of the pull-down transistor. The leakage currents of all the pull-up transistors need to be smaller than this pull-down current when all the pull-up paths are off. The ratio of these off-currents can be adjusted by the aspect ratios of the transistors. The logic type offers extremely low current consumption with low voltages and offers the possibility to avoid more complex shut-down circuitry often used in ultra low-power designs. The logic type offers higher operation speed compared to the existing solutions.

公开(公告)号：US09843328B1

公开(公告)日：2017-12-12

申请号：US15173507

申请日：2016-06-03

申请人： Altera Corporation

发明人： Ping Xiao

IPC分类号： H03K19/017 ,  H03K19/177 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H03K19/1774 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16155 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/18161 ,  H03K17/223 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/17708

摘要： A 3D field programmable gate array (FPGA) system, and method of manufacture therefor, includes: a field programmable gate array (FPGA) die having a configurable power on reset (POR) unit; a heterogeneous integrated circuit die coupled to the FPGA die; and a 3D power on reset (POR) output configured by the configurable POR unit for initializing the FPGA die and the heterogeneous integrated circuit die.

公开(公告)号：US20170264296A1

公开(公告)日：2017-09-14

申请号：US15066205

申请日：2016-03-10

申请人： VIA Alliance Semiconductor Co., Ltd.

发明人： Yeong-Sheng LEE

IPC分类号： H03K19/0185 ,  H03K19/003 ,  H03K19/017 ,  H03K19/00

CPC分类号： H03K19/018507 ,  H03K19/0013 ,  H03K19/00315 ,  H03K19/017

摘要： A pre-driver for driving an LVDS (Low Voltage Differential Signaling) driving circuit is provided. The pre-driver includes a first inverter, a high-pass filter, and a second inverter. The first inverter has an input terminal coupled to an input node of the pre-driver, and an output terminal coupled to a first node. The high-pass filter is coupled between the first node and a second node. The second inverter has an input terminal coupled to the second node, and an output terminal coupled to an output node of the pre-driver. The high-pass filter is configured to improve a high-frequency response of the pre-driver.

公开(公告)号：US09742404B2

公开(公告)日：2017-08-22

申请号：US14822402

申请日：2015-08-10

申请人： Silicon Works Co., Ltd.

发明人： Seung Jong Lee ,  Young Jin Woo ,  Hoo Hyun Cho

IPC分类号： H03L5/00 ,  H03K19/00 ,  H03K19/017 ,  H03K19/0185

CPC分类号： H03K19/0013 ,  H03K19/01714 ,  H03K19/018521 ,  H03K19/018528

摘要： A level shifter circuit with improved time response and a control method thereof are disclosed herein. The level shifter circuit includes the output stage circuit of a level shifter and a booster circuit. The output stage circuit of the level shifter includes a first pass switch configured to transfer a voltage level of the first power supply of the level shifter to an output node, and a second pass switch connected between a second power supply and the first pass switch. The booster circuit accelerates the switching operation of the level shifter by accelerating a time response during the turning on or off operation of the first pass switch using charge sharing between a first capacitor and the parasitic capacitance of the control node of the first pass switch, which occurs via a first switch.

公开(公告)号：US20170154568A1

公开(公告)日：2017-06-01

申请号：US15361213

申请日：2016-11-25

申请人： LAPIS Semiconductor Co., Ltd.

发明人： Hiroshi TSUCHI

IPC分类号： G09G3/20 ,  H03K19/017 ,  G11C19/00 ,  H03K19/0185

CPC分类号： G09G3/2092 ,  G09G2300/043 ,  G09G2300/0809 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2330/06 ,  G11C19/00 ,  H03K19/017 ,  H03K19/018521

摘要： A level shift circuit configured to generate an output signal having higher amplitude than that of an input signal. The level shift circuit includes serially-connected first and second level shift circuit for two-step amplitude increase of the input signal. The first level shift circuit includes first to fourth transistors, each of which has a control terminal and first and second current terminals, and first and second resistance elements respectively connected between the first and third transistors, and between the second and fourth transistors. A potential difference between two ends of each resistance element is respectively smaller than, or no smaller than, a respective predetermined potential difference when a current does not flow, or flows, therethrough. The second level shift circuit has fifth to tenth transistors, each of which has a control terminal and first and second current terminals. The output signal is outputted through a connection between the second current terminals of the fifth and ninth transistors.