公开(公告)号：US20190129718A1

公开(公告)日：2019-05-02

申请号：US15799560

申请日：2017-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Jiasheng Chen ,  Bin He ,  Yunxiao Zou ,  Michael J. Mantor ,  Radhakrishna Giduthuri ,  Eric J. Finger ,  Brian D. Emberling

IPC: G06F9/30 ,  G06F7/483

Abstract: Systems, apparatuses, and methods for routing traffic between clients and system memory are disclosed. A computing system includes a processor capable of executing single precision mathematical instructions on data sizes of M bits and half precision mathematical instructions on data sizes of N bits, which is less than M bits. At least two source operands with M bits indicated by a received instruction are read from a register file. If the instruction is a packed math instruction, at least a first source operand with a size of N bits less than M bits is selected from either a high portion or a low portion of one of the at least two source operands read from the register file. The instruction includes fields storing bits, each bit indicating the high portion or the low portion of a given source operand associated with a register identifier specified elsewhere in the instruction.

公开(公告)号：US20190123648A1

公开(公告)日：2019-04-25

申请号：US16130136

申请日：2018-09-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Huang ,  Yasuko Eckert ,  Xudong An ,  Muhammad Shoaib Bin Altaf ,  Jieming Yin

IPC: H02M3/158 ,  G05F1/56 ,  G05F1/46

CPC classification number: H02M3/1582 ,  G05F1/468 ,  G05F1/56 ,  G05F1/575 ,  H02M2001/0022

Abstract: The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. The switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of the circuits in the set of circuits. During operation, a controller sets an operating point for each of the subsets of circuits based on a combined power efficiency for the subsets of the circuits and the LDO regulators, each operating point including a corresponding frequency and voltage.

公开(公告)号：US20190122417A1

公开(公告)日：2019-04-25

申请号：US16179376

申请日：2018-11-02

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mark Fowler ,  Timothy Kelley ,  Mikko Alho ,  Mika Tuomi ,  Kiia Kallio ,  Patrick Klas Rudolf Buss ,  Jari Antero Komppa ,  Kaj Tuomi

IPC: G06T15/00

Abstract: A system, method and a non-transitory computer readable storage medium are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from one or more primitives. A bin is identified for processing the primitive batch. At least a portion of each primitive intersecting the identified bin is processed and a next bin for processing the primitive batch is identified based on an intercept walk order. The processing is iteratively repeated for the one or more primitives in the primitive batch for successive bins until all primitives of the primitive batch are completely processed. Then, the one or more primitives in the primitive batch are further processed.

公开(公告)号：US10255191B2

公开(公告)日：2019-04-09

申请号：US15133033

申请日：2016-04-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini-Farahani ,  David A. Roberts

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/14 ,  G06F3/06 ,  G06F12/02

Abstract: Systems, apparatuses, and methods for implementing logical memory address regions in a computing system. The physical memory address space of a computing system may be partitioned into a plurality of logical memory address regions. Each logical memory address region may be dynamically configured at run-time to meet changing application needs of the system. Each logical memory address region may also be configured separately from the other logical memory address regions. Each logical memory address region may have associated parameters that identify region start address, region size, cell-level mode, physical-to-device mapping scheme, address masks, access permissions, wear-leveling data, encryption settings, and compression settings. These parameters may be stored in a table which may be used when processing memory access requests.

公开(公告)号：US20190101638A1

公开(公告)日：2019-04-04

申请号：US15721457

申请日：2017-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Ngoc Vinh Vu ,  Neil Patrick Kelly

IPC: G01S13/89 ,  H04N7/20 ,  H04N5/44 ,  H04N5/38 ,  G01S7/00

Abstract: Systems, apparatuses, and methods for implementing a dual-purpose millimeter-wave frequency band transmitter are disclosed. A system includes a dual-purpose transmitter sending a video stream over a wireless link to a receiver. In some embodiments, the video stream is generated as part of an augmented reality (AR) or virtual reality (VR) application. The transmitter operates in a first mode to scan and map an environment of the transmitter and receiver. The transmitter generates radio frequency (RF) signals in a first frequency range while operating in the first mode. Additionally, the transmitter operates in a second mode to send video data to the receiver, and the transmitter generates RF signals in the first frequency range while operating in the second mode.

公开(公告)号：US10248177B2

公开(公告)日：2019-04-02

申请号：US14919364

申请日：2015-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Miguel Rodriguez ,  Stephen Victor Kosonocky

IPC: G06F1/32 ,  G06F1/30 ,  G06F1/26 ,  G06F1/3234 ,  G06F1/3287

Abstract: A processor system includes first and second regulators for regulating an adjusted supply voltage. The first and second regulators generate a plurality of control signals to regulate an adjusted power supply voltage and that generate a charge when a droop level falls below a droop threshold value by implementing first and second control loops. A supply adjustment block with the two regulators and control loops are provided for each processor core allowing different cores to have different regulated supply levels all based on one common supply. One regulator is a global regulator while another is a local regulator found in each of the processing tiles. Processing tiles are grouped into two groups wherein one group includes tiles that may powered down to save power. Voltage rails of the two groups are selectively connected to equalize voltage levels when both groups are powered on and operating.

公开(公告)号：US10247770B2

公开(公告)日：2019-04-02

申请号：US15381992

申请日：2016-12-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Abhay Deshpande ,  Arun S. Iyer ,  Prasanth K. Vallur ,  Girish Anathahally Singrigowda ,  Stephen V. Kosonocky

IPC: G01R31/26 ,  H03K5/159 ,  H03K3/03

Abstract: Various embodiments of a gate oxide breakdown detection technique detect gate oxide degradation due to stress on a per part basis without destroying functional circuits for an intended application. Stress on the gate oxide may be applied while nominal drain currents flow through a device, thereby stressing the device under conditions similar to actual operating conditions. The technique is relatively fast and does not require analog amplifiers or tuning of substantial amounts of other additional circuitry as compared to conventional gate oxide breakdown detection techniques.

公开(公告)号：US10243727B2

公开(公告)日：2019-03-26

申请号：US14529238

申请日：2014-10-31

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Winthrop Wu ,  James Goodman ,  Martin Kiernicki ,  Yoichi Shimokawa ,  William Thomas Morrison ,  Creighton Eldridge ,  David Kaplan

IPC: H04K1/00 ,  H04L9/00 ,  G09C1/00 ,  H04L9/06 ,  H04L9/30

Abstract: The present disclosure presents methods, apparatuses, and systems to bolster communication security, and more particularly to utilize a constant time cryptographic co-processor engine for such communication security. For example, the disclosure includes a method for secure communication, comprising receiving encrypted data at a receiving device; obtaining a randomization for at least one bit of the encrypted data; modifying an execution of a cryptographic algorithm on the at least one bit to obtain a randomized cryptographic algorithm based on the randomization; and executing the randomized cryptographic algorithm on the at least one bit of encrypted data to recover original data associated with the encrypted data.

公开(公告)号：US10242962B1

公开(公告)日：2019-03-26

申请号：US15669361

申请日：2017-08-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Thomas P. Dolbear ,  Daniel Cavasin ,  Sanjay Dandia

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L21/48 ,  H01L21/78 ,  H01L25/065 ,  C23C16/06 ,  C23C16/34

Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin.

公开(公告)号：US20190076618A1

公开(公告)日：2019-03-14

申请号：US15840310

申请日：2017-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Evgene Fainstain

IPC: A61M21/00 ,  G06F3/01 ,  G06T11/60

Abstract: Described herein are a method, system and apparatus for mitigating motion sickness in a virtual reality (VR) environment. In an implementation, the system and apparatus can include a VR controller board, a processor and a VII headset. In an implementation, the processor and VR headset are an integrated device. In general, the method includes capturing measurements using the VR controller board. The measurements are indicative of user directional movements in a physical environment relative to the VR environment. In an implementation, the measurements relate to changes in the location of the center of mass of the user relative to the VR controller board. The processor uses the measurements to determine predetermined actions in the VR environment. The predetermined actions are then executed in the VR environment nearly simultaneous with the user directional movements in the physical environment.