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公开(公告)号：US10204915B1
公开(公告)日：2019-02-12
申请号：US15894840
申请日：2018-02-12
Inventor： Yu-Shan Su , Chia-Wei Wu
IPC: H01L27/108 , H01L21/28 , H01L21/02 , H01L29/51 , H01L21/311 , H01L29/66 , H01L29/49 , H01L21/3105
Abstract: A method of forming a dynamic random access memory (DRAM) includes the following steps. A substrate includes a memory area and a logic area. A stacked structure is formed on the substrate of the memory area and a gate structure is formed on the substrate of the logic area. A first mask layer is formed on the stacked structure and the gate structure. A densification process is performed to densify the first mask layer. A second mask layer is formed on the first mask layer. A part of the second mask layer and a part of the first mask layer are removed to form a first spacer on sidewalls of the gate structure.
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公开(公告)号：US10204911B2
公开(公告)日：2019-02-12
申请号：US15859763
申请日：2018-01-02
Inventor： Chieh-Te Chen , Feng-Yi Chang , Fu-Che Lee
IPC: H01L21/033 , H01L21/311 , H01L27/108 , H01L21/02 , H01L49/02 , H01L21/027
Abstract: A method for fabricating a capacitor includes providing a substrate and a first etching stop layer on the substrate; forming a plurality of first spacers on the first etching stop layer; forming an organic layer and a second etching stop layer sequentially on the first spacers, the organic layer covering the first spacers; forming a plurality of second spacers on the second etching stop layer, each second spacer crossing the first spacers; transferring a pattern of the second spacers to the organic layer to form an organic pattern; performing an etching process using the organic pattern and the first spacers as a mask to form an etching stop pattern and remove the second etching stop layer; transferring the etching stop pattern to the substrate to form a plurality of through holes.
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公开(公告)号：US10203596B2
公开(公告)日：2019-02-12
申请号：US14989765
申请日：2016-01-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： En-Chiuan Liou , Che-Yi Lin
Abstract: A method of filtering overlay data by field is provided in the present invention. The method includes the following steps. A minimum number of measure points per field on a semiconductor substrate is decided. Field data filtering rules are set. Overlay raw data is inputted. A raw data filtration is performed to the overlay raw data by field according to the field data filtering rules. Modified exposure parameters are generated for each field according to overlay data of remaining measure points per field after the raw data filtration when the number of the remaining measure points per field is larger than or equal to the minimum number of the measure points per field. Accordingly, the modified exposure parameters will be more effective in reducing the overlay error because more outliers may be filtered out before generating the modified exposure parameters.
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公开(公告)号：US20190043863A1
公开(公告)日：2019-02-07
申请号：US16158321
申请日：2018-10-12
Inventor： Yukihiro Nagai , Le-Tien Jung
IPC: H01L27/102 , H01L29/66 , H01L21/768 , H01L29/87 , H01L23/535 , H01L29/06 , H01L21/762
Abstract: A semiconductor device includes a substrate having a cell region and a peripheral region, a thyristor on the cell region, a MOS transistor on the peripheral region, and a first silicide layer on the substrate adjacent to the thyristor on the cell region. Preferably, the thyristor includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the cell region, vertical dielectric patterns in the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer, and first contact plugs on the fourth semiconductor layer.
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公开(公告)号：US20190043729A1
公开(公告)日：2019-02-07
申请号：US15698765
申请日：2017-09-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung
IPC: H01L21/3105 , H01L27/088 , H01L21/8234 , H01L23/00 , H01L23/522
CPC classification number: H01L21/31053 , H01L21/823475 , H01L23/522 , H01L23/5228 , H01L23/564 , H01L27/0629 , H01L27/088
Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate having an active component region and a non-active component region, a first dielectric layer, a second dielectric layer, high resistivity metal segments, dummy stacked structures and a metal connection structure. The high resistivity metal segments are formed in the second dielectric layer and located in the non-active component region. The dummy stacked structures are located in the non-active component region, and at least one dummy stacked structure penetrates through the first dielectric layer and the second dielectric layer and is located between two adjacent high resistivity metal segments. The metal connection structure is disposed on the second dielectric layer, and the high resistivity metal segments are electrically connected to one another through the metal connection structure.
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Patent Agency Ranking
公开(公告)号：US10199485B2
公开(公告)日：2019-02-05
申请号：US15409467
申请日：2017-01-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Ying Lin , Chueh-Yang Liu , Yu-Ren Wang
IPC: H01L29/06 , H01L29/775 , H01L29/78 , H01L29/08 , H01L29/12 , H01L29/165 , H01L29/66 , H01L21/265 , H01L21/306
Abstract: A semiconductor device includes a substrate including a first semiconductor material, a gate structure formed on the substrate, and a source stressor and a drain stressor formed in the substrate respectively in a recess at two sides of the gate structure. The source stressor and the drain stressor respectively include at least a first quantum wire and at least a second quantum wire formed on the first quantum wire. The first quantum wire includes the first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. And the second quantum wire includes the second semiconductor material.
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公开(公告)号：US10199385B1
公开(公告)日：2019-02-05
申请号：US15665437
申请日：2017-08-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kuo-Lung Li , Ping-Chia Shih , Wen-Peng Hsu , Chia-Wen Wang , Meng-Chun Chen , Chih-Hao Pan
IPC: H01L27/115 , H01L27/11568 , H01L29/423 , H01L29/792 , H01L21/28 , H01L29/66
Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.
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公开(公告)号：US10199258B2
公开(公告)日：2019-02-05
申请号：US15384940
申请日：2016-12-20
Inventor： Chieh-Te Chen , Hsien-Shih Chu , Ming-Feng Kuo , Fu-Che Lee , Chien-Ting Ho , Chiung-Lin Hsu , Feng-Yi Chang , Yi-Wang Zhan , Li-Chiang Chen , Chien-Cheng Tsai , Chin-Hsin Chiu
IPC: H01L21/762 , H01L21/308
Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.
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公开(公告)号：US10186594B2
公开(公告)日：2019-01-22
申请号：US15641312
申请日：2017-07-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Ting Chiang , Chi-Ju Lee , Chih-Wei Lin , Bo-Yu Su , Yen-Liang Wu , Wen-Tsung Chang , Jui-Ming Yang , I-Fan Chang
Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.
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公开(公告)号：US20190019731A1
公开(公告)日：2019-01-17
申请号：US15647031
申请日：2017-07-11
Applicant: United Microelectronics Corp.
Inventor： Ching-Ling Lin , Wen-An Liang , Chen-Ming Huang
IPC: H01L21/8234 , H01L21/033
Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.
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