公开(公告)号：US10170994B1

公开(公告)日：2019-01-01

申请号：US15682900

申请日：2017-08-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Thomas J. Gibney ,  Larry D. Hewitt ,  Daniel L. Bouvier

IPC: H02M3/158 ,  H02M3/139

Abstract: The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. During operation, the switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of circuits in the set of circuits.

公开(公告)号：US10158712B2

公开(公告)日：2018-12-18

申请号：US14730837

申请日：2015-06-04

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Eric Christopher Morton

IPC: G06F15/16 ,  H04L29/08 ,  G06F3/06

Abstract: A technique for source-side memory request network admission control includes adjusting, by a first node, a rate of injection of memory requests by the first node into a network coupled to a memory system. The adjusting is based on an injection policy for the first node and memory request efficiency indicators. The method may include injecting memory requests by the first node into the network coupled to the memory system. The injecting has the rate of injection. The technique includes adjusting the rate of injection by the first node. The first node adjusts the rate of injection according to an injection policy for the first node and memory request efficiency indicators. The injection policy may be based on an injection rate limit for the first node. The injection policy for the first node may be based on an injection rate limit per memory channel for the first node. The technique may include determining the memory request efficiency indicators based on comparisons of target addresses of the memory requests to addresses of recent memory requests of the first node.

公开(公告)号：US10158530B2

公开(公告)日：2018-12-18

申请号：US14461614

申请日：2014-08-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael E. James ,  Jean-Philippe Fricker

IPC: G06F15/177 ,  H04L12/24 ,  H04L12/753 ,  G06F15/173

Abstract: A cluster computer server is configured after a system reset or other configuration event. Each node of a fabric of the cluster compute server is employed, for purposes of configuration, as a cell in a cellular automaton, thereby obviating the need for a special configuration network to communicate configuration information from a central management unit. Instead, the nodes communicate configuration information using the same fabric interconnect that is used to communicate messages during normal execution of software services at the nodes.

公开(公告)号：US20180358080A1

公开(公告)日：2018-12-13

申请号：US15618349

申请日：2017-06-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei HUANG

IPC: G11C11/4078 ,  H01L27/108 ,  H01L23/38 ,  H01L35/32 ,  H01L27/16

CPC classification number: G11C7/04 ,  H01L23/38 ,  H01L27/10897 ,  H01L27/16 ,  H01L35/32

Abstract: Managing temperature of a semiconductor device having a temperature inverted processor core and stacked memory by operation of an integrated thermoelectric cooler. The thermoelectric cooler is operated to pump heat from a stacked memory device that requires a cool operating temperature to a temperature inverted processor core that maintains a higher operating temperature until threshold operating temperatures are achieved.

公开(公告)号：US10152602B2

公开(公告)日：2018-12-11

申请号：US14748883

申请日：2015-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： David Kaplan ,  Leendert van Doorn ,  Joshua Schiffman

IPC: G06F9/455 ,  G06F21/60 ,  G06F12/14 ,  G06F12/1036 ,  G06F21/53

Abstract: A processing system includes a processor that implements registers to define a state of a virtual machine (VM) running on the processor. The processor detects exit conditions of the VM. The processing system also includes a memory element to store contents of the registers in a first data structure that is isolated from a hypervisor of the VM in response to the processor detecting an exit condition. The VM is to selectively expose contents of a subset of the registers to the hypervisor.

公开(公告)号：US20180349215A1

公开(公告)日：2018-12-06

申请号：US15614498

申请日：2017-06-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Shuai Che

IPC: G06F9/54

Abstract: Techniques for managing message transmission in a large networked computer system that includes multiple individual networked computing systems are disclosed. Message passing among the computing systems include a sending computing device transmitting a message to a receiver computing device and a receiver computing device consuming that message. A build-up of data stored in a buffer at the receiver can reduce performance. In order to reduce the potential performance degradation associated with large amounts of “waiting” data in the buffer, a sending computer system first determines whether the receiver computer system is ready to receive a message and does not transmit the message if the receiver computer system is not ready. To determine whether the receiver computer system is ready to receive a message, the receiver computer system, at the request of the sending computer system, checks a counting filter that stores indications of whether particular messages are ready.

公开(公告)号：US20180343430A1

公开(公告)日：2018-11-29

申请号：US15605474

申请日：2017-05-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael L. Schmit ,  Radhakrishna Giduthuri ,  Kiriti Nagesh Gowda

IPC: H04N13/00 ,  G06T15/20 ,  G06F3/01 ,  G06T3/40 ,  H04N5/225 ,  H04N13/02

CPC classification number: H04N13/117 ,  G06T3/4038 ,  H04N5/2254 ,  H04N5/2258 ,  H04N5/23238 ,  H04N5/247 ,  H04N13/204 ,  H04N13/243

Abstract: A method and apparatus of precomputing includes capturing a first image by a first image capturing device. An image space for the first image is defined and pixels in the image space are analyzed for validity. Valid pixels are stored as valid pixel groups and the valid pixel groups are processed.

公开(公告)号：US20180342099A1

公开(公告)日：2018-11-29

申请号：US16057212

申请日：2018-08-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Timour T. Paltashev ,  Boris Prokopenko ,  Vladimir V. Kibardin

IPC: G06T17/20 ,  G06T1/20 ,  G06T15/00

CPC classification number: G06T17/20 ,  G06T1/20 ,  G06T15/005 ,  G06T2210/52

Abstract: A method, a system, and a computer-readable storage medium directed to performing high-speed parallel tessellation of 3D surface patches are disclosed. The method includes generating a plurality of primitives in parallel. Each primitive in the plurality is generated by a sequence of functional blocks, in which each sequence acts independently of all the other sequences.

公开(公告)号：US20180341613A1

公开(公告)日：2018-11-29

申请号：US15605291

申请日：2017-05-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  Michael Ignatowski

IPC: G06F13/40 ,  G06F13/16 ,  G11C5/02 ,  G11C5/06 ,  G11C7/06 ,  G11C5/14

Abstract: A method and apparatus of integrating memory stacks includes providing a first memory die of a first memory technology and a second memory die of a second memory technology. A first logic die is in communication with the first memory die of the first memory technology, and includes a first memory controller including a first memory control function for interpreting requests in accordance with a first protocol for the first memory technology. A second logic die is in communication with the second memory die of the second memory technology and includes a second memory controller including a second memory control function for interpreting requests in accordance with a second protocol for the second memory technology. A memory operation request is received at the first or second memory controller, and the memory operation request is performed in accordance with the associated first memory protocol or the second memory protocol.

公开(公告)号：US20180329842A1

公开(公告)日：2018-11-15

申请号：US16042912

申请日：2018-07-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Greg Sadowski

IPC: G06F13/28 ,  G06F13/42 ,  G06F1/32

CPC classification number: G06F13/28 ,  G06F1/3203 ,  G06F1/3287 ,  G06F13/4282 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: A method of and device for removing a processor from a low power mode. The method includes and the device provides for performing multiple processor start-up tasks in parallel. Memory interface training between the processor and memory and restoration and initialization of the processor are performed in parallel with each other and with a serial bus controller entering serial bus training to facilitate communication between the processor and a system controller.