公开(公告)号：US10762010B2

公开(公告)日：2020-09-01

申请号：US15808595

申请日：2017-11-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US10734064B1

公开(公告)日：2020-08-04

申请号：US15992100

申请日：2018-05-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4091 ,  G06F12/14 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4072 ,  G11C29/38 ,  G11C29/32 ,  G11C29/22 ,  G11C5/04

Abstract: A memory control component has control circuitry and a data interface, the data interface to be coupled, via a plurality of data signaling paths, to a respective plurality of memory dies disposed on a memory module. The control circuitry transmits to the memory module a first configuration value that specifies a memory die quantity N that is permitted to range from a first value corresponding to the quantity of the data signaling paths to at least one value less than the first value. Thereafter, the control circuitry transmits a memory read command to the memory module to enable, in accordance with the first configuration value, a quantity N of the memory dies to output read data and enables the data interface to receive the read data via a respective quantity N of the data signaling paths.

公开(公告)号：US10705989B2

公开(公告)日：2020-07-07

申请号：US15864732

申请日：2018-01-08

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Holden Jessup

IPC: G06F13/16

Abstract: The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.

公开(公告)号：US10672450B2

公开(公告)日：2020-06-02

申请号：US16139636

申请日：2018-09-24

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C8/00 ,  G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234 ,  G11C11/4074

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US10656851B2

公开(公告)日：2020-05-19

申请号：US16372336

申请日：2019-04-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06F13/16 ,  G06Q10/00 ,  G11C7/02 ,  G11C11/406 ,  G06Q20/00

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

公开(公告)号：US10650872B2

公开(公告)日：2020-05-12

申请号：US16215573

申请日：2018-12-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Brian S. Leibowitz ,  Wayne Frederick Ellis ,  Akash Bansal ,  John Welsford Brooks ,  Kishore Ven Kasamsetty

IPC: G06F12/00 ,  G11C8/18 ,  G11C29/02 ,  G06F13/16 ,  G11C7/10 ,  G11C5/02 ,  G06F13/42 ,  G11C5/04

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

公开(公告)号：US10565049B2

公开(公告)日：2020-02-18

申请号：US15646025

申请日：2017-07-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G06F12/02

Abstract: A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction location including an error code bit location. Logic retrieves and stores the tag information associated with the row in response to activation of the row. A bit error in an accessed data column is repaired by a spare bit location based on the tag information.

公开(公告)号：US20200051610A1

公开(公告)日：2020-02-13

申请号：US16549992

申请日：2019-08-23

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Frederick A. Ware

IPC: G11C11/4076 ,  G11C7/22 ,  G11C7/10 ,  G06F13/42 ,  G06F1/04

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

公开(公告)号：US10475505B2

公开(公告)日：2019-11-12

申请号：US15872840

申请日：2018-01-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C11/4093 ,  G11C5/04 ,  H01L25/065 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  H01L25/18 ,  H01L23/00

Abstract: A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.

公开(公告)号：US10467157B2

公开(公告)日：2019-11-05

申请号：US15376507

申请日：2016-12-12

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G06F13/16

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.