公开(公告)号：US20190294378A1

公开(公告)日：2019-09-26

申请号：US16371345

申请日：2019-04-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Thomas Vogelsang

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/02 ,  G11C7/10

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

公开(公告)号：US20190277909A1

公开(公告)日：2019-09-12

申请号：US16357122

申请日：2019-03-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G01R31/28 ,  H03L7/00 ,  G11C29/16 ,  G11C29/50 ,  G01R31/26 ,  G11C29/12 ,  G11C29/02 ,  G01R31/317

Abstract: A memory controller instantiated on a semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The memory controller further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

公开(公告)号：US10409742B2

公开(公告)日：2019-09-10

申请号：US15284307

申请日：2016-10-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright

IPC: G06F11/00 ,  G06F13/16 ,  G06F11/07 ,  G06F13/40

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

公开(公告)号：US20190259435A1

公开(公告)日：2019-08-22

申请号：US16344321

申请日：2017-10-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/00 ,  G11C14/00 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0895 ,  G11C5/04

Abstract: A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.

公开(公告)号：US10360972B2

公开(公告)日：2019-07-23

申请号：US15552569

申请日：2016-02-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Scott C. Best ,  Kenneth L. Wright

IPC: G11C5/02 ,  G11C11/4093 ,  G11C5/06 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/00 ,  H01L25/065 ,  H01L25/10 ,  G11C11/4096 ,  H01L25/18 ,  G11C7/10 ,  G11C8/12 ,  H01L23/00

Abstract: A memory system includes dynamic random-access memory (DRAM) component that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US10339990B2

公开(公告)日：2019-07-02

申请号：US15665312

申请日：2017-07-31

Applicant: Rambus Inc.

Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

IPC: G01C7/02 ,  G11C7/22 ,  G06F13/16 ,  G11C7/02

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

公开(公告)号：US20190180805A1

公开(公告)日：2019-06-13

申请号：US16215573

申请日：2018-12-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Brian S. Leibowitz ,  Wayne Frederick Ellis ,  Akash Bansal ,  John Welsford Brooks ,  Kishore Ven Kasamsetty

IPC: G11C8/18 ,  G06F13/16 ,  G11C7/10 ,  G11C29/02 ,  G06F13/42 ,  G11C5/02

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

公开(公告)号：US10268619B2

公开(公告)日：2019-04-23

申请号：US15169275

申请日：2016-05-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kishore Kasamsetty

IPC: G06F13/40 ,  G06F12/02 ,  G06F13/16 ,  G06F12/00 ,  G06F3/06 ,  G06F13/42 ,  G11C5/02

Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.

公开(公告)号：US20190115059A1

公开(公告)日：2019-04-18

申请号：US15555470

申请日：2016-03-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt

IPC: G11C11/00 ,  G11C7/12 ,  G11C7/10 ,  G06F3/06 ,  G06F11/10

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile memory devices, and a buffer disposed between the pin interface and the at least two non-volatile memory devices. The buffer receives non-volatile memory access commands from the memory controller that are interleaved with DRAM memory module access commands.

公开(公告)号：US10223309B2

公开(公告)日：2019-03-05

申请号：US15533630

申请日：2015-10-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G06F13/16 ,  G11C7/10 ,  G11C5/04

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.