-
公开(公告)号：US20230205547A1
公开(公告)日：2023-06-29
申请号：US17564557
申请日：2021-12-29
申请人： ATI Technologies ULC
发明人： Kamraan Nasim , Erez Koelewyn
IPC分类号： G06F9/4401 , G06F9/48 , G06F9/54
CPC分类号： G06F9/4406 , G06F9/4843 , G06F9/546 , G06F2209/548
摘要： A system and method for efficiently measuring on-die power supply voltage are described. In various implementations, an integrated circuit includes at least one or more processors and on-chip memory. The on-chip memory has a higher security level than off-chip memory. One of the one or more processors is designated as a security processor. During the processing of the multiple boot steps of a bootup operation, the security processor initializes a message queue in on-chip memory. The security processor also loads multiple modules from off-chip memory into the on-chip memory. The processor executes the multiple loaded modules in an order based on using the message queue to implement inter-module communication among the plurality of boot modules. The security processor transfers requested data between modules using messages from the modules and data storage of the message queue. The modules are completed without reloading any modules from off-chip memory.
-
公开(公告)号：US20230205306A1
公开(公告)日：2023-06-29
申请号：US17561837
申请日：2021-12-24
IPC分类号： G06F1/3296
CPC分类号： G06F1/3296
摘要： One or more components of a computing device are run by default in a boost mode state. The one or more components continue to run in the boost mode state until the boost mode state is no longer sustainable, e.g., due to power consumption of the one or more components or temperature of the one or more components. The one or more components are switched to a reduced power state (e.g., a non-boost mode state) in response to the boost mode state no longer being sustainable. When operating the one or more components in the boost mode state again becomes sustainable due to power consumption or temperature of the one or more components, the one or more components are returned to the default boost mode state.
-
公开(公告)号：US11687251B2
公开(公告)日：2023-06-27
申请号：US17487247
申请日：2021-09-28
CPC分类号： G06F3/0619 , G06F3/064 , G06F3/0644 , G06F3/0659 , G06F3/0673 , G06F12/0607
摘要： Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.
-
公开(公告)号：US20230198528A1
公开(公告)日：2023-06-22
申请号：US17557590
申请日：2021-12-21
CPC分类号： H03L7/0805 , H03L7/085
摘要： A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.
-
公开(公告)号：US20230196496A1
公开(公告)日：2023-06-22
申请号：US17555955
申请日：2021-12-20
申请人： ATI Technologies ULC
发明人： David I.J. Glen
CPC分类号： G06T1/20 , G06F3/14 , G06F3/04847
摘要： An image generation apparatus includes at least a first configuration register that includes first configuration data for configuring parameters of an image processor, at least a second configuration register that includes second configuration data for configuring the parameters of a same image processing pipeline in the image processor, multiplexing logic coupled to the first configuration register and to the second configuration register, control logic that controls the multiplexing logic to in a non-demonstration mode select one of the first or second configuration registers to produce a first image frame and operative in a demonstration mode to provide both the first and second configuration data for the same image processing pipeline of the image processor to use for generating different regions of an image frame.
-
公开(公告)号：US11682465B2
公开(公告)日：2023-06-20
申请号：US17491164
申请日：2021-09-30
申请人： ATI Technologies ULC
发明人： Zheng Gong , Jiao Wang , Zhenhua Yang
CPC分类号： G11C17/16 , G11C17/18 , G11C29/027 , G11C29/44 , H01L23/481 , H01L23/5256 , H10B20/20
摘要： An integrated circuit includes a TSV extending from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate and having a first end and a second end, and a non-volatile repair circuit. The non-volatile repair circuit includes a one-time programmable (OTP) element having a programming terminal, wherein in response to an application of a fuse voltage to the programming terminal, the OTP element electrically couples the first end of the TSV to the second end of the TSV.
-
公开(公告)号：US20230161632A1
公开(公告)日：2023-05-25
申请号：US17486332
申请日：2021-09-27
IPC分类号： G06F9/50
CPC分类号： G06F9/5044 , G06F9/505 , G06F9/5016 , G06F9/5038
摘要： Compound processing of an upscaler operation using platform resources includes: identifying a plurality of platform resources available to perform an upscaling operation, wherein the plurality of platform resources includes one or more graphics processor units (GPUs) and one or more accelerated processing units (APUs); and dynamically assigning workloads of the upscaling operation to one or more of the platform resources based on a modality of the upscaling operation; and processing the workloads of the upscaling operation by the platform resources to which the workloads are assigned.
-
公开(公告)号：US20230156205A1
公开(公告)日：2023-05-18
申请号：US18099095
申请日：2023-01-19
申请人： ATI Technologies ULC
IPC分类号： H04N19/426 , H04N19/176 , H04N19/119 , H04N19/46 , H04N19/60 , H04N19/96 , H04N19/154 , H04N19/54 , G06T9/00 , H04N19/182
CPC分类号： H04N19/426 , H04N19/176 , H04N19/119 , H04N19/46 , H04N19/60 , H04N19/96 , H04N19/154 , H04N19/54 , G06T9/00 , H04N19/182
摘要： A system and method for texture decompression is described. The method comprises receiving a first compressed texture block including two or more disjoint subsets of data and decompressing the first compressed texture block. The decompressing includes decompressing the two or more disjoint subsets in the first compressed texture block to form texels. The two or more disjoint subsets include a first disjoint subset comprising a first set of color endpoints and a second disjoint subset comprising a second set of color endpoints.
-
公开(公告)号：US20230148254A1
公开(公告)日：2023-05-11
申请号：US18089837
申请日：2022-12-28
申请人： ATI TECHNOLOGIES ULC
CPC分类号： G09G5/00 , G06T1/20 , G06T9/00 , G09G2330/023 , G09G2360/18 , G09G2370/12
摘要： A graphics processing unit (GPU) of a processing system transmits pixel data for a frame to a display in a compressed burst, so that the pixel data is communicated at a rate that is higher than the rate at which the display scans out the pixel data to refresh the frame at a display panel. By transmitting pixel data for the frame in a compressed burst, the GPU shortens the time spent transmitting the pixel data and extends the time before the next frame of pixel data is to be transmitted. During the extended time before the next frame of pixel data is to be transmitted, the GPU saves power by placing portions of the processing system in a reduced power mode.
-
公开(公告)号：US11640711B2
公开(公告)日：2023-05-02
申请号：US17030250
申请日：2020-09-23
发明人： Nicholas Malaya , Max Kiehn
摘要： A technique for generating a trained discriminator is provided. The technique includes applying one or more of a glitched image or an unglitched image to a discriminator; receiving classification output from the discriminator; adjusting weights of the discriminator to improve classification accuracy of the discriminator; applying noise to a generator; receiving an output image from the generator; applying the output image to the discriminator to obtain a classification; and adjusting weights of one of the discriminator or the generator to improve ability of the generator to reduce classification accuracy of the discriminator, based on the classification.
-
-
-
-
-
-
-
-
-
搜索结果
1753 条记录 (耗时 0.036 秒)
