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    Printed, self-aligned, top gate thin film transistor
    71.
    发明申请
    Printed, self-aligned, top gate thin film transistor 有权
    印刷，自对准，顶栅薄膜晶体管

    公开(公告)号：US20070287237A1

    公开(公告)日：2007-12-13

    申请号：US11818078

    申请日：2007-06-12

    Applicant: Joerg Rockenberger ,  James Cleeves ,  Arvind Kamath

    Inventor： Joerg Rockenberger ,  James Cleeves ,  Arvind Kamath

    IPC: H01L21/84 ,  H01L21/00

    CPC classification number: H01L29/7866 ,  B82Y10/00 ,  H01L27/1248 ,  H01L27/1292 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78681 ,  H01L29/7869

    Abstract: A self-aligned top-gate thin film transistor (TFT) and a method of forming such a thin film transistor, by forming a semiconductor thin film layer; printing a doped glass pattern thereon, a gap in the doped glass pattern defining a channel region of the TFT; forming a gate electrode on or over the channel region, the gate electrode comprising a gate dielectric film and a gate conductor thereon; and diffusing a dopant from the doped glass pattern into the semiconductor thin film layer.

    Abstract translation: 一种自对准顶栅薄膜晶体管（TFT）和通过形成半导体薄膜层形成这种薄膜晶体管的方法; 在其上印刷掺杂的玻璃图案，所述掺杂玻璃图案中的间隙限定所述TFT的沟道区域; 在沟道区域上或上方形成栅电极，栅电极在其上包括栅介质膜和栅极导体; 并且将掺杂剂从掺杂的玻璃图案扩散到半导体薄膜层中。

    METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT
    72.
    发明授权
    METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT 有权
    在混合集成电路的某些晶体管中减少硅氧烷栅绝缘体厚度的方法，以获得具有混合电路的其他晶体管的栅绝缘体厚度增加的差异

    公开(公告)号：US06521549B1

    公开(公告)日：2003-02-18

    申请号：US09724225

    申请日：2000-11-28

    Applicant: Arvind Kamath ,  Rajiv Patel ,  Ravindra M. Kapre

    Inventor： Arvind Kamath ,  Rajiv Patel ,  Ravindra M. Kapre

    IPC: H01L21469

    CPC classification number: H01L21/823462

    Abstract: A relatively thin gate insulator of a digital switching transistor is formed from a layer of silicon oxynitride which was initially formed by implanting nitrogen atoms in a silicon substrate and oxidizing the nitrogen and silicon. It has been discovered that an outer layer of silicon dioxide is formed as a part of the silicon oxynitride layer. Removing this outer layer of silicon dioxide from the silicon oxynitride layer leaves a thin remaining layer of substantially-only silicon oxynitride as the gate insulator. Thinner gate insulators of approximately 15-21 angstroms, for example, can be formed from a grown thickness of 60 angstroms, for example. Gate insulators for digital and analog transistors may be formed simultaneously with a greater differential in thickness been possible by using conventional nitrogen implantation techniques.

    Abstract translation: 数字开关晶体管的相对薄的栅极绝缘体由氮氧化硅层形成，其最初通过在硅衬底中注入氮原子并氧化氮和硅而形成。 已经发现，作为氧氮化硅层的一部分形成二氧化硅的外层。 从氮氧化硅层中除去二氧化硅外层留下基本上只有氮氧化硅的薄剩余层作为栅极绝缘体。 例如，大约15-21埃的较薄的栅极绝缘体可以由例如60埃的生长厚度形成。 用于数字和模拟晶体管的栅极绝缘体可以同时形成，通过使用常规氮注入技术，可以获得更大的厚度差。

    LASER PATTERNED SOLID-STATE BATTERIES, AND METHODS OF MAKING AND USING THE SAME
    74.
    发明申请
    LASER PATTERNED SOLID-STATE BATTERIES, AND METHODS OF MAKING AND USING THE SAME 有权

    公开(公告)号：US20240379932A1

    公开(公告)日：2024-11-14

    申请号：US18640416

    申请日：2024-04-19

    Applicant: Khanh TRAN ,  Alex Yan ,  Arvind KAMATH ,  Zhongchun WANG

    Inventor： Khanh TRAN ,  Alex Yan ,  Arvind KAMATH ,  Zhongchun WANG

    IPC: H01M4/04 ,  H01M4/76 ,  H01M10/0525 ,  H01M10/0562

    Abstract: A method of making a lithium metal oxide film is disclosed. The method includes blanket-depositing a cathode material, a solid-state electrolyte, and an anode current collector (ACC) material on a substrate, laser-patterning the ACC material to define the solid-state battery cells and form an ACC in each of the cells, and cutting or dicing the solid-state battery cells through the electrolyte and the cathode material to form a cathode in each of the solid-state battery cells. The method avoids issues related to topography and wet patterning when making the cathode, electrolyte and ACC layers. The method also avoids the need to fabricate a physical mask, thereby enabling greater patterning flexibility, higher throughput and lower costs than photolithography.

    Surveillance Devices with Multiple Capacitors
    79.
    发明申请
    Surveillance Devices with Multiple Capacitors 有权
    具有多个电容器的监控设备

    公开(公告)号：US20140091909A1

    公开(公告)日：2014-04-03

    申请号：US13632745

    申请日：2012-10-01

    Applicant: Patrick SMITH ,  Criswell CHOI ,  James Montague CLEEVES ,  Vivek SUBRAMANIAN ,  Arvind KAMATH ,  Steven MOLESA

    Inventor： Patrick SMITH ,  Criswell CHOI ,  James Montague CLEEVES ,  Vivek SUBRAMANIAN ,  Arvind KAMATH ,  Steven MOLESA

    IPC: G06K7/01 ,  H01G7/00 ,  G06K19/077

    CPC classification number: H01G4/40 ,  H01G4/38

    Abstract: The present invention relates to surveillance and/or identification devices having capacitors connected in parallel or in series, and methods of making and using such devices. Devices with capacitors connected in parallel, where one capacitor is fabricated with a relatively thick capacitor dielectric and another is fabricated with a relatively thin capacitor dielectric achieve both a high-precision capacitance and a low breakdown voltage for relatively easy surveillance tag deactivation. Devices with capacitors connected in series result in increased lateral dimensions of a small capacitor. This makes the capacitor easier to fabricate using techniques that may have relatively limited resolution capabilities.

    Abstract translation: 本发明涉及具有并联或串联连接的电容器的监视和/或识别装置以及制造和使用这些装置的方法。 具有并联连接电容器的器件，其中一个电容器用相对较厚的电容器电介质制造，另一个电容器由相对薄的电容器电介质制成，实现了高精度电容和低击穿电压，以便相对容易的监视标签去激活。 具有串联连接的电容器的装置增加了小电容器的横向尺寸。 这使得使用可能具有相对有限的分辨能力的技术来制造电容器更容易。

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