公开(公告)号：US06230400B1

公开(公告)日：2001-05-15

申请号：US09398940

申请日：1999-09-17

申请人： George Tzanavaras ,  Mihalis Michael

发明人： George Tzanavaras ,  Mihalis Michael

IPC分类号： H05K334

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L23/4334 ,  H01L24/11 ,  H01L24/16 ,  H01L29/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/351 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49213 ,  H01L2924/00

摘要： An embodiment of the present invention is a method for wafer level IC packaging that includes the steps of: (a) forming compliant, conductive bumps on metalized bond pads or conductors; and (b) surrounding the compliant, conductive bumps in a supporting layer.

摘要翻译： 本发明的一个实施例是一种用于晶片级IC封装的方法，包括以下步骤：（a）在金属化接合焊盘或导体上形成柔顺的导电凸块; 和（b）在支撑层中包围柔性导电凸块。

公开(公告)号：US06555759B2

公开(公告)日：2003-04-29

申请号：US09791488

申请日：2001-02-21

申请人： George Tzanavaras ,  Mihalis Michael

发明人： George Tzanavaras ,  Mihalis Michael

IPC分类号： H05K116

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L23/4334 ,  H01L24/11 ,  H01L24/16 ,  H01L29/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/351 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49213 ,  H01L2924/00

摘要： An embodiment of the present invention is a method for wafer level IC packaging that includes the steps of: (a) forming compliant, conductive bumps on metalized bond pads or conductors; and (b) surrounding the compliant, conductive bumps in a supporting layer.

摘要翻译： 本发明的一个实施例是一种用于晶片级IC封装的方法，包括以下步骤：（a）在金属化接合焊盘或导体上形成柔顺的导电凸块; 和（b）在支撑层中包围柔性导电凸块。

公开(公告)号：US20230420731A1

公开(公告)日：2023-12-28

申请号：US18319552

申请日：2023-05-18

申请人： Khanh TRAN ,  Arvind KAMATH ,  Richard VAN DER LINDE ,  Yasumasa MORITA ,  Zhongchun WANG ,  Mihalis MICHAEL

发明人： Khanh TRAN ,  Arvind KAMATH ,  Richard VAN DER LINDE ,  Yasumasa MORITA ,  Zhongchun WANG ,  Mihalis MICHAEL

IPC分类号： H01M10/0562 ,  H01M10/052 ,  H01M10/058 ,  H01M4/66 ,  H01M4/131 ,  H01M4/136 ,  H01M50/562

CPC分类号： H01M10/0562 ,  H01M10/052 ,  H01M10/058 ,  H01M50/562 ,  H01M4/131 ,  H01M4/136 ,  H01M4/661

摘要： A solid-state battery and methods of making the same are disclosed. The battery includes a plurality of cells and first and second terminals on opposite sides/edges of the battery. Each cell includes a cathode current collector (CCC), a cathode thereon, a solid-state electrolyte, an anode current collector (ACC), a barrier/insulation film, a via/opening in the barrier/insulation film exposing the ACC, and a conductive redistribution layer on the ACC in the via/opening, on the barrier/insulation film, and on a first sidewall of each cell. The barrier/insulation film encapsulates the CCC, the cathode, the solid-state electrolyte and the ACC. The first sidewall of each cell is on one of the sides/edges of the battery. One terminal is electrically connected to each ACC through the redistribution layer, and the other is electrically connected to each cathode or CCC.

公开(公告)号：US09070662B2

公开(公告)日：2015-06-30

申请号：US12716197

申请日：2010-03-02

申请人： Mihalis Michael ,  Ilija Jergovic

发明人： Mihalis Michael ,  Ilija Jergovic

IPC分类号： H01L23/367 ,  H01L23/42 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/3675 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/42 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/75 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2731 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/75745 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/838 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92242 ,  H01L2224/97 ,  H01L2224/98 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/0401

摘要： A semiconductor package can include a semiconductor die having an integrated circuit, a first die surface, and an opposite second die surface. A packaging can be attached to the die and have a holder surface opposite the first die surface. A heat spreader can be configured to cover the second die surface and the packaging surface and can be attached thereto by a layer of adhesive positioned between the heat spreader and the semiconductor die. A semiconductor package array can include an array of semiconductor dies and a heat spreader configured to cover each semiconductor die. A conductive lead can be electrically connected to the integrated circuit in a semiconductor die and can extend from the first die surface. Manufacturing a semiconductor package can include applying thermally conductive adhesive to the heat spreader and placing the heat spreader proximate the semiconductor die.

摘要翻译： 半导体封装可以包括具有集成电路的半导体管芯，第一管芯表面和相对的第二管芯表面。 包装可以附接到模具并且具有与第一模具表面相对的保持器表面。 散热器可以被配置为覆盖第二模具表面和包装表面，并且可以通过位于散热器和半导体管芯之间的粘合剂层附接到散热器。 半导体封装阵列可以包括半导体管芯阵列和配置成覆盖每个半导体管芯的散热器。 导电引线可以与半导体管芯中的集成电路电连接并且可以从第一管芯表面延伸。 制造半导体封装可以包括将热传导粘合剂施加到散热器并将散热器放置在半导体管芯附近。

公开(公告)号：US06778390B2

公开(公告)日：2004-08-17

申请号：US09858823

申请日：2001-05-15

申请人： Mihalis Michael

发明人： Mihalis Michael

IPC分类号： H05K720

CPC分类号： H01L23/467 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus and method are described for cooling electronic components on a plug-in or other computer board placed within an enclosure. The inventive apparatus and system is capable of cooling a high power dissipating device, such as a Graphics Processing Unit and cooling individual ones of a plurality of other devices, such as memory chips, to within a specified temperature range. In one embodiment, cooling air is drawn from the edge of a plug-in card, over the GPU and is directed along and over arrays of memory chips. By directing the flow on and along the memory chips, a flow is established that maintains the chip-to-chip temperature difference to within a desired, uniform range. The invention allows for the incorporation of higher performance processors onto boards while maintaining memory chips within a temperature range that allows for predictable performance.

摘要翻译： 描述了用于冷却放置在外壳内的插件或其它计算机板上的电子部件的装置和方法。 本发明的装置和系统能够冷却诸如图形处理单元的高功率​​耗散装置，并且将诸如存储器芯片的多个其他装置中的各个装置冷却到指定的温度范围内。 在一个实施例中，冷却空气从插件卡的边缘被抽出，在GPU上并沿着存储芯片阵列引导。 通过在存储器芯片上引导流程，建立了将芯片间温度差保持在期望的均匀范围内的流程。 本发明允许在板上并入更高性能的处理器，同时将存储器芯片保持在允许可预测性能的温度范围内。

公开(公告)号：US20240113341A1

公开(公告)日：2024-04-04

申请号：US18468606

申请日：2023-09-15

申请人： RICHARD VAN DER LINDE ,  Arvind KAMATH ,  Khanh TRAN ,  Yasumasa MORITA ,  Zhongchun WANG ,  Mihalis MICHAEL

发明人： RICHARD VAN DER LINDE ,  Arvind KAMATH ,  Khanh TRAN ,  Yasumasa MORITA ,  Zhongchun WANG ,  Mihalis MICHAEL

IPC分类号： H01M10/0587 ,  H01M4/13 ,  H01M4/66 ,  H01M50/107 ,  H01M50/109 ,  H01M50/548

CPC分类号： H01M10/0587 ,  H01M4/13 ,  H01M4/661 ,  H01M50/107 ,  H01M50/109 ,  H01M50/548

摘要： A cylindrical solid-state battery and methods of making the same are disclosed. The battery includes a solid-state battery cell wound, wrapped or rolled around a core or itself, first and second terminals on opposite ends of the battery, and packaging between the first and second terminals, sealing the cell therein. The cell comprises a cathode current collector (CCC), a cathode on the CCC, a solid-state electrolyte on the cathode, an anode current collector (ACC) on the electrolyte, an insulation film on the ACC with an opening therein exposing the ACC, and a conductive redistribution layer in the opening and on the insulation film and a first sidewall of the cell. One of the terminals is electrically connected to the ACC through the redistribution layer, and the other terminal is electrically connected to the cathode or CCC on the opposite end of the battery.

公开(公告)号：US20230378606A1

公开(公告)日：2023-11-23

申请号：US18319532

申请日：2023-05-18

申请人： Khanh TRAN ,  Mihalis MICHAEL ,  Yasumasa MORITA ,  Shahid PIRZADA ,  Richard van der LINDE ,  Arvind KAMATH

发明人： Khanh TRAN ,  Mihalis MICHAEL ,  Yasumasa MORITA ,  Shahid PIRZADA ,  Richard van der LINDE ,  Arvind KAMATH

IPC分类号： H01M50/446 ,  H01M10/052 ,  H01M4/66 ,  H01M4/131 ,  H01M4/136 ,  H01M10/0562 ,  H01M50/417 ,  H01M50/562 ,  H01M10/058

CPC分类号： H01M50/446 ,  H01M10/052 ,  H01M4/661 ,  H01M4/131 ,  H01M4/136 ,  H01M10/0562 ,  H01M4/663 ,  H01M50/417 ,  H01M50/562 ,  H01M10/058

摘要： A solid-state battery and methods of making the same are disclosed. The battery includes a plurality of cells and first and second terminals on opposite sides/edges of the battery. Each cell includes a cathode current collector (CCC), a cathode thereon, a solid-state electrolyte, an anode current collector (ACC), a moat in the cathode and the electrolyte and around the ACC, a barrier/insulation film, a via/opening in the barrier/insulation film exposing the ACC, and a conductive redistribution layer in the via/opening, in the moat, on the barrier/insulation film, and on a first sidewall of each cell. The barrier/insulation film encapsulates the CCC, the cathode, the solid-state electrolyte and the ACC. One terminal is electrically connected to each ACC through the redistribution layer, and the other is electrically connected to each cathode or CCC.

公开(公告)号：US20100224985A1

公开(公告)日：2010-09-09

申请号：US12716197

申请日：2010-03-02

申请人： Mihalis Michael ,  Ilija Jergovic

发明人： Mihalis Michael ,  Ilija Jergovic

IPC分类号： H01L23/367 ,  H01L23/52 ,  H01L23/50 ,  H01L21/50 ,  H01L23/538

CPC分类号： H01L23/3675 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/42 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/75 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2731 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/75745 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/838 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92242 ,  H01L2224/97 ,  H01L2224/98 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/0401

摘要： A semiconductor package can include a semiconductor die having an integrated circuit, a first die surface, and an opposite second die surface. A packaging can be attached to the die and have a holder surface opposite the first die surface. A heat spreader can be configured to cover the second die surface and the packaging surface and can be attached thereto by a layer of adhesive positioned between the heat spreader and the semiconductor die. A semiconductor package array can include an array of semiconductor dies and a heat spreader configured to cover each semiconductor die. A conductive lead can be electrically connected to the integrated circuit in a semiconductor die and can extend from the first die surface. Manufacturing a semiconductor package can include applying thermally conductive adhesive to the heat spreader and placing the heat spreader proximate the semiconductor die.

摘要翻译： 半导体封装可以包括具有集成电路的半导体管芯，第一管芯表面和相对的第二管芯表面。 包装可以附接到模具并且具有与第一模具表面相对的保持器表面。 散热器可以被配置为覆盖第二模具表面和包装表面，并且可以通过位于散热器和半导体管芯之间的粘合剂层附接到散热器。 半导体封装阵列可以包括半导体管芯阵列和配置成覆盖每个半导体管芯的散热器。 导电引线可以与半导体管芯中的集成电路电连接并且可以从第一管芯表面延伸。 制造半导体封装可以包括将热传导粘合剂施加到散热器并将散热器放置在半导体管芯附近。

公开(公告)号：US06214640B1

公开(公告)日：2001-04-10

申请号：US09366152

申请日：1999-08-03

申请人： Jennifer Fosberry ,  Masud Beroz ,  Mihalis Michael ,  Philip Osborn

发明人： Jennifer Fosberry ,  Masud Beroz ,  Mihalis Michael ,  Philip Osborn

IPC分类号： H01L2144

CPC分类号： H01L23/3121 ,  H01L21/56 ,  H01L21/561 ,  H01L23/16 ,  H01L23/24 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/40 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/86 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A method of manufacturing a plurality of semiconductor chips packages and the resulting chip package assemblies. The method includes providing a circuitized substrate having terminals and leads. A spacer layer is deposited or attached to the substrate and each chip is then attached to the spacer layer. Typically, the spacer layer is comprised of a compliant or resilient material. The terminals and leads are interconnected using leads, at least some of which are fan-out leads. A ring-like pattern of a curable composition is disposed around each chip and cured to form a support structure. The assembly is encapsulated by dispensing a composition which is curable to an encapsulant into the gaps between the support structures and the chips. The encapsulant material is then cured thereby defining a composite of chip assemblies which may be singulated into individual chip packages.

摘要翻译： 一种制造多个半导体芯片封装的方法和所得到的芯片封装组件。 该方法包括提供具有端子和引线的电路化基板。 将间隔层沉积或附着到基底上，然后将每个芯片附接到间隔层。 通常，间隔层由顺应性或弹性材料构成。 端子和引线使用引线互连，其中至少一些是扇出引线。 可固化组合物的环状图案设置在每个芯片周围并固化以形成支撑结构。 通过将可固化到密封剂的组合物分配到支撑结构和芯片之间的间隙中来封装组件。 密封剂材料然后被固化，从而限定了可以被分成单个芯片封装的芯片组件的复合材料。