中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

255 records (took 0.021 seconds)

    METHOD AND APPARATUS FOR COST AND POWER EFFICIENT, SCALABLE OPERATING SYSTEM INDEPENDENT SERVICES
    71.
    发明申请
    METHOD AND APPARATUS FOR COST AND POWER EFFICIENT, SCALABLE OPERATING SYSTEM INDEPENDENT SERVICES 有权
    成本和功率有效的可扩展操作系统独立服务的方法和装置

    公开(公告)号：US20120192000A1

    公开(公告)日：2012-07-26

    申请号：US13436835

    申请日：2012-03-30

    Applicant: Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

    Inventor： Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

    IPC: G06F1/00

    CPC classification number: G06F1/3287 ,  G06F1/3209 ,  Y02D10/171

    Abstract: A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is applied for a short period of time to an execution subsystem and one of a plurality of cores selected to handle processing of received service requests. After processing the received service requests, the computer system returns to the lowest power state.

    Abstract translation: 提供了低成本，低功耗的可扩展架构，以允许在所有系统电源状态期间远程管理计算机系统。 在最低功率状态下，功率仅适用于检查网络分组所需的最小逻辑。 将电力短时间施加到执行子系统，并且被选择用于处理所接收的服务请求的处理的多个核心中的一个。 在处理接收到的服务请求之后，计算机系统返回到最低功率状态。

    ELECTRICAL MASK INSPECTION
    73.
    发明申请
    ELECTRICAL MASK INSPECTION 失效
    电磁屏蔽检查

    公开(公告)号：US20120068174A1

    公开(公告)日：2012-03-22

    申请号：US12886612

    申请日：2010-09-21

    Applicant: Arvind Kumar ,  Anthony I-Chih Chou ,  Shreesh Narasimha

    Inventor： Arvind Kumar ,  Anthony I-Chih Chou ,  Shreesh Narasimha

    IPC: H01L23/522 ,  H01L21/66 ,  H01L21/768

    CPC classification number: H01L23/544 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain.

    Abstract translation: 公开了一种用于电气掩模检查的装置和方法。 在两个金属层和通孔层之间形成扫描链。 三层之一是被测功能层，另外两层是测试层。 使用扫描链的电阻测量来确定在包括扫描链的通孔或金属段之一内是否存在潜在缺陷。

    Stator turn fault detection apparatus and method for induction machine
    74.
    发明授权
    Stator turn fault detection apparatus and method for induction machine 有权
    感应电机定子转动故障检测装置及方法

    公开(公告)号：US08140291B2

    公开(公告)日：2012-03-20

    申请号：US12365118

    申请日：2009-02-03

    Applicant: Bogdan Z. Kasztenny ,  Somakumar Ramachandrapanicker ,  Arvind Kumar Tiwari ,  Arijit Banerjee

    Inventor： Bogdan Z. Kasztenny ,  Somakumar Ramachandrapanicker ,  Arvind Kumar Tiwari ,  Arijit Banerjee

    IPC: G05R31/00

    CPC classification number: G01R31/34 ,  G01R31/025 ,  G01R31/346

    Abstract: A system and method are provided for correction of parameters used in determination of stator turn faults of an induction motor. An embodiment may include determining a residual impedance and/or a residual voltage of the motor, and correcting a normalized cross-coupled impedance based on the residual impedance and residual voltage. Additional embodiments may include measuring an operating temperature of the motor and determining a negative sequence impedance of the motor based on the temperature. Another embodiment may include measuring voltages and currents of the motor and determining phasors for the voltages and currents using compensation for variations from a nominal frequency of the motor.

    Abstract translation: 提供了用于校正用于确定感应电动机的定子匝故障的参数的系统和方法。 实施例可以包括确定电动机的残余阻抗和/或剩余电压，以及基于残余阻抗和残余电压校正归一化的交叉耦合阻抗。 另外的实施例可以包括测量电动机的工作温度并基于温度确定电动机的负序阻抗。 另一个实施例可以包括测量电动机的电压和电流，并且使用对来自电动机的额定频率的变化的补偿来确定电压和电流的相量。

    Structure and method for manufacturing asymmetric devices
    75.
    发明授权
    Structure and method for manufacturing asymmetric devices 有权
    用于制造不对称装置的结构和方法

    公开(公告)号：US08034692B2

    公开(公告)日：2011-10-11

    申请号：US12581924

    申请日：2009-10-20

    Applicant: Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

    Inventor： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

    IPC: H01L21/336

    CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66659

    Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

    Abstract translation: 在基板上形成多个栅极结构。 每个栅极结构包括第一栅极电极和源极和漏极区域。 从每个栅极结构去除第一栅电极。 施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。 在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。 去除第一光致抗蚀剂。 施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。 在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。 去除第二光致抗蚀剂。 在每个栅极结构中形成替代栅电极。

    BULK SUBSTRATE FET INTEGRATED ON CMOS SOI
    76.
    发明申请
    BULK SUBSTRATE FET INTEGRATED ON CMOS SOI 有权
    集成在CMOS SOI上的基极FET

    公开(公告)号：US20110163383A1

    公开(公告)日：2011-07-07

    申请号：US12683456

    申请日：2010-01-07

    Applicant: Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    Inventor： Anthony I. Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Ning Su ,  Huiling Shang

    IPC: H01L27/12 ,  H01L21/86

    CPC classification number: H01L27/1207 ,  H01L21/84

    Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.

    Abstract translation: 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

    Mounting a heat sink in thermal contact with an electronic component
    77.
    发明授权
    Mounting a heat sink in thermal contact with an electronic component 有权
    安装与电子元件热接触的散热片

    公开(公告)号：US07944698B2

    公开(公告)日：2011-05-17

    申请号：US12164367

    申请日：2008-06-30

    Applicant: John Lee Colbert ,  Eric Alan Eckberg ,  Roger Duane Hamilton ,  Mark Kenneth Hoffmeyer ,  Amanda Elisa Ennis Mikhail ,  Arvind Kumar Sinha

    Inventor： John Lee Colbert ,  Eric Alan Eckberg ,  Roger Duane Hamilton ,  Mark Kenneth Hoffmeyer ,  Amanda Elisa Ennis Mikhail ,  Arvind Kumar Sinha

    IPC: H05K7/20

    CPC classification number: H01L23/4006 ,  H01L2023/405 ,  H01L2023/4081 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/4913 ,  Y10T29/49826 ,  H01L2924/00

    Abstract: A heat transfer apparatus comprises a load frame having load springs and an open region that exposes an electronic component. The load frame is mounted to a printed circuit board on which the electronic component is mounted. A heat sink assembly is disposed on the load frame and has a main body in thermal contact with the electronic component through a thermally conductive material. The heat sink assembly has load arms for engaging the load springs. A load plate extends between the load arms and has an actuation element operative to displace the main body relative to the load plate and thereby resiliently deform the load springs and produce a load force that compresses the thermally conductive material to achieve a desired thermal interface gap between the main body and the electronic component. Non-influencing fasteners secure the heat sink to the load frame and maintain the desired thermal interface gap.

    Abstract translation: 传热装置包括具有负载弹簧的负载框架和暴露电子部件的开放区域。 负载框架安装在其上安装电子部件的印刷电路板上。 散热器组件设置在负载框架上，并且具有通过导热材料与电子部件热接触的主体。 散热器组件具有用于接合负载弹簧的负载臂。 负载板在负载臂之间延伸并且具有致动元件，该致动元件可操作地相对于负载板移动主体，从而使负载弹簧弹性变形，并产生负载力，该负载力压缩导热材料以实现期望的热界面间隙 主体和电子部件。 不影响的紧固件将散热器固定到负载框架上并保持所需的热接口间隙。

    Field effect transistor containing a wide band gap semiconductor material in a drain
    78.
    发明授权
    Field effect transistor containing a wide band gap semiconductor material in a drain 有权
    在漏极中含有宽带隙半导体材料的场效应晶体管

    公开(公告)号：US07936042B2

    公开(公告)日：2011-05-03

    申请号：US11939017

    申请日：2007-11-13

    Applicant: Arvind Kumar

    Inventor： Arvind Kumar

    IPC: H01L29/02

    CPC classification number: H01L21/26586 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7848

    Abstract: A field effect transistor comprising a silicon containing body is provided. After formation of a gate dielectric, gate electrode, and a first gate spacer, a drain side trench is formed and filled with a wide band gap semiconductor material. Optionally, a source side trench may be formed and filled with a silicon germanium alloy to enhance an on-current of the field effect transistor. Halo implantation and source and drain ion implantation are performed to form various doped regions. Since the wide band gap semiconductor material as a wider band gap than that of silicon, impact ionization is reduced due to the use of the wide band gap semiconductor material in the drain, and consequently, a breakdown voltage of the field effect transistor is increased compared to transistors employing silicon in the drain region.

    Abstract translation: 提供了包括硅含量体的场效应晶体管。 在形成栅极电介质，栅极电极和第一栅极间隔物之后，形成漏极侧沟槽并填充宽带隙半导体材料。 可选地，可以形成源极沟槽并填充硅锗合金以增强场效应晶体管的导通电流。 进行光晕注入和源极和漏极离子注入以形成各种掺杂区域。 由于宽带隙半导体材料作为比硅的带隙宽的带隙，由于在漏极中使用宽带隙半导体材料，因此冲击电离降低，因此，场效应晶体管的击穿电压比较 涉及在漏极区域中使用硅的晶体管。

    Substrate solution for back gate controlled SRAM with coexisting logic devices
    79.
    发明授权
    Substrate solution for back gate controlled SRAM with coexisting logic devices 有权
    用于具有共存逻辑器件的背栅控制SRAM的衬底解决方案

    公开(公告)号：US07838942B2

    公开(公告)日：2010-11-23

    申请号：US12144272

    申请日：2008-06-23

    Applicant: Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

    Inventor： Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

    IPC: H01L29/76

    CPC classification number: H01L27/1108

    Abstract: A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

    Abstract translation: 一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂 提供了特定的水平，以提高不同器件区域内的FET器件的性能。 特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。 为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。 在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。

Patent Agency Ranking