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    Tilt device for vehicular steering column
    71.
    发明授权
    Tilt device for vehicular steering column 有权

    公开(公告)号：US07127963B2

    公开(公告)日：2006-10-31

    申请号：US10241706

    申请日：2002-09-12

    Applicant: Byeong-Hoon Lee

    Inventor： Byeong-Hoon Lee

    IPC: B62D1/18

    CPC classification number: B62D1/184

    Abstract: The present invention relates to a tilt device for a vehicular steering column, which permits a lock slider cooperating with an operating lever to regulate pivoting of a movable gear by simplifying the engagement structure between the movable gear and a fixed gear to reduce the number of parts and enhance assembling ability, thereby reducing manufacturing cost. The tilt device of the invention also minimizes the operating force of the operating lever while elevating the coupling force between the operating lever and a lock slider so as to improve convenience of users.

    Duty cycle correction circuit
    72.
    发明申请
    Duty cycle correction circuit 审中-公开
    占空比校正电路

    公开(公告)号：US20060114042A1

    公开(公告)日：2006-06-01

    申请号：US11286686

    申请日：2005-11-23

    Applicant: Heon-soo Lee ,  Byeong-hoon Lee

    Inventor： Heon-soo Lee ,  Byeong-hoon Lee

    IPC: H03K3/017

    CPC classification number: H03K5/1565 ,  H03K5/086

    Abstract: There is provided a compact duty cycle correction circuit including minimal components for generating a signal with a 50% duty cycle. The duty cycle correction circuit includes a storage element and a correction circuit. The storage element generates an output signal in response to a clock signal and a feedback signal. The correction circuit includes a resistor and a capacitor and outputs the feedback signal in response to the output signal of the storage element.

    Abstract translation: 提供了一种紧凑的占空比校正电路，其包括用于产生具有50％占空比的信号的最小组件。 占空比校正电路包括存储元件和校正电路。 存储元件响应于时钟信号和反馈信号产生输出信号。 校正电路包括电阻器和电容器，并且响应于存储元件的输出信号而输出反馈信号。

    Semiconductor memory device with reduced chip area and improved redundancy efficency
    73.
    发明授权
    Semiconductor memory device with reduced chip area and improved redundancy efficency 失效
    半导体存储器件具有减少的芯片面积和提高的冗余效率

    公开(公告)号：US06944085B2

    公开(公告)日：2005-09-13

    申请号：US10376757

    申请日：2003-02-27

    Applicant: Byeong-Hoon Lee ,  Seung-Keun Lee

    Inventor： Byeong-Hoon Lee ,  Seung-Keun Lee

    IPC: G11C16/06 ,  G11C16/04 ,  G11C29/00 ,  G11C29/04 ,  G11C8/00

    CPC classification number: G11C29/789 ,  G11C16/0441 ,  G11C29/808

    Abstract: A redundancy circuit embedded in the semiconductor memory device includes a sector selector and a bit line selector. The bit line selector repairs defective bit lines and the sector selector repairs defective global bit lines and selectively repairs defective bit lines. The sector selector includes a fixed address cell storage box for storing addresses of the defective bit lines and a flexible address cell storage box for storing addresses of the defective global bit lines. The circuit area is minimized since the coding unit corresponding to a sector address is not included in the bit line selector. The repair rate of defective bit lines is improved since the sector selector operates selectively as the bit line selector.

    Abstract translation: 嵌入在半导体存储器件中的冗余电路包括扇区选择器和位线选择器。 位线选择器修复有缺陷的位线，并且扇区选择器修复缺陷的全局位线，并选择性地修复有缺陷的位线。 扇区选择器包括用于存储有缺陷位线的地址的固定地址单元存储盒和用于存储缺陷全局位线的地址的灵活地址单元存储盒。 由于与扇区地址相对应的编码单元不包括在位线选择器中，所以电路区域被最小化。 由于扇区选择器选择性地作为位线选择器操作，故障位线的修复率得到改善。

    Charge pump circuit for use in high voltage generating circuit
    74.
    发明授权
    Charge pump circuit for use in high voltage generating circuit 有权
    用于高压发生电路的电荷泵电路

    公开(公告)号：US06690227B2

    公开(公告)日：2004-02-10

    申请号：US10055269

    申请日：2002-01-22

    Applicant: Byeong-Hoon Lee ,  Seung-Keun Lee ,  Seung-Won Lee

    Inventor： Byeong-Hoon Lee ,  Seung-Keun Lee ,  Seung-Won Lee

    IPC: G05F110

    CPC classification number: H02M3/073 ,  H02M2003/078

    Abstract: A charge pump circuit includes a plurality of serially connected pump stages. Each pump stage includes current paths connected between a gate terminal of a charge transfer transistor and a drain terminal thereof. One of the charge transfer paths allows charges to be transferred from the drain terminal to the gate terminal while the other path allows charges to be transferred from the gate terminal to the drain terminal. The charge pump circuit can generate a high target voltage using a very low power supply voltage (e.g., 2V or lower).

    Abstract translation: 电荷泵电路包括多个串联连接的泵级。 每个泵级包括连接在电荷转移晶体管的栅极端子和其漏极端子之间的电流路径。 电荷转移路径之一允许电荷从漏极端子传送到栅极端子，而另一路径允许电荷从栅极端子传输到漏极端子。 电荷泵电路可以使用非常低的电源电压（例如2V或更低）产生高目标电压。

    Semiconductor memory device row decoder structures having reduced layout area, and methods of operating the same
    75.
    发明授权
    Semiconductor memory device row decoder structures having reduced layout area, and methods of operating the same 失效
    具有减小布局面积的半导体存储器件行解码器结构及其操作方法

    公开(公告)号：US06665229B2

    公开(公告)日：2003-12-16

    申请号：US10122131

    申请日：2002-04-11

    Applicant: Byeong-Hoon Lee ,  Seung-Keun Lee

    Inventor： Byeong-Hoon Lee ,  Seung-Keun Lee

    IPC: G11C800

    CPC classification number: G11C8/14 ,  G11C8/08 ,  G11C8/10 ,  G11C16/08 ,  G11C16/30 ,  G11C2216/18

    Abstract: Semiconductor memory device row decoder structures have reduced layout area. A structure for erasing memory cells coupled to a single bitline includes a single bias driver for these cells, and a plurality of local voltage level converters coupled to the bias driver. At least one word line driver is coupled to each local level converter, to erase at least one of the memory cells. A global word line is also coupled to the word line driver. A method for erasing these memory cells includes biasing the local level converter, for powering in turn a component of the word line driver. In addition, an existing global word line driver powers another component of the word line driver, thus resulting in reduced design requirements for the local level converter.

    Abstract translation: 半导体存储器件行解码器结构具有减小的布局面积。 用于擦除耦合到单个位线的存储器单元的结构包括用于这些单元的单个偏置驱动器和耦合到偏置驱动器的多个局部电压电平转换器。 至少一个字线驱动器耦合到每个局部电平转换器，以擦除至少一个存储器单元。 全局字线也耦合到字线驱动器。 用于擦除这些存储单元的方法包括偏置本地电平转换器，从而依次为字线驱动器的部件供电。 此外，现有的全局字线驱动器为字线驱动器的另一个组件供电，从而导致局部级转换器的设计要求降低。

    Sense amplifier circuit for a flash memory device
    76.
    发明授权
    Sense amplifier circuit for a flash memory device 失效
    用于闪存器件的感测放大器电路

    公开(公告)号：US06490199B2

    公开(公告)日：2002-12-03

    申请号：US09867899

    申请日：2001-05-30

    Applicant: Byeong-Hoon Lee ,  Young-Ho Lim

    Inventor： Byeong-Hoon Lee ,  Young-Ho Lim

    IPC: G11C1606

    CPC classification number: G11C16/28

    Abstract: A sense amplifier circuit for a flash memory device of the present invention includes first and second pre-charge circuits for pre-charging a data line (or bit line connected electrically to the data line). The first and second pre-charge circuits are each connected to the data line. The first pre-charge circuit provides a current changed by a fluctuation of the data line voltage to the data line, and the second pre-charge circuit provides a constant voltage regardless of the fluctuation of the data line voltage to the data line. The sense amplifier minimizes the time required to pre-charge the data line (or bit line) to a desired voltage.

    Abstract translation: 本发明的闪存器件的读出放大器电路包括用于对数据线（或与数据线电连接的位线）进行预充电的第一和第二预充电电路。 第一和第二预充电电路各自连接到数据线。 第一预充电电路提供由数据线电压向数据线的波动而改变的电流，并且第二预充电电路提供恒定电压，而不管数据线电压对数据线的波动。 读出放大器将数据线（或位线）预充电所需的时间最小化到所需的电压。

    Flash memory system operating in a random access mode
    79.
    发明授权
    Flash memory system operating in a random access mode 有权
    闪存系统以随机存取模式运行

    公开(公告)号：US08259501B2

    公开(公告)日：2012-09-04

    申请号：US13006068

    申请日：2011-01-13

    Applicant: Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

    Inventor： Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

    IPC: G11C16/04

    CPC classification number: G11C16/0483

    Abstract: A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory.

    Abstract translation: 存储器系统包括操作以控制存储器的存储器和存储器控制器。 存储器包括随机存取存储器，其包括以随机存取模式操作的存储单元阵列，NAND闪速存储器和使存储器控制器操作随机存取存储器或NAND闪速存储器之一的选择电路。

    Method and apparatus of correcting error data caused by charge loss within non-volatile memory device
    80.
    发明授权
    Method and apparatus of correcting error data caused by charge loss within non-volatile memory device 有权
    在非易失性存储器件内纠正由电荷损失引起的误差数据的方法和装置

    公开(公告)号：US08108755B2

    公开(公告)日：2012-01-31

    申请号：US12010244

    申请日：2008-01-23

    Applicant: Seung-won Lee ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

    Inventor： Seung-won Lee ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

    IPC: G01F11/10 ,  G11C29/00

    CPC classification number: G11C16/3431 ,  G06F11/1068 ,  G11C16/3418 ,  G11C2029/0411

    Abstract: Example embodiments provide a method and apparatus of correcting error data due to charge loss within a non-volatile memory device including a plurality of memory cells. The method of correcting error data within the non-volatile memory devices may include detecting error data in a second data group by comparing a first data group read from memory cells in response to a first voltage with the second data group read from memory cells in response to a second voltage. The second voltage is higher than the first voltage. Error data in the first data group is detected by error-correcting code (ECC). Re-writing data in the memory cells is performed by correcting error data in the first data group and error data in the second data group. A central processing unit (CPU) may detect error in the second data group. The second data group may be read through a page buffer and compared with the first data group stored in a SRAM. The detected error may be updated to the page buffer. Error data in the first data group may be updated to the page buffer. The CPU corrects error in the final error data, and the page buffer rewrites the corrected data in the plurality of memory cells.

    Abstract translation: 示例性实施例提供了一种在包括多个存储器单元的非易失性存储器件内由于电荷损失而校正误差数据的方法和装置。 校正非易失性存储器件中的错误数据的方法可以包括通过将响应于第一电压的存储器单元读取的第一数据组与从存储器单元读取的第二数据组进行响应来检测第二数据组中的错误数据 到第二电压。 第二电压高于第一电压。 通过纠错码（ECC）检测第一数据组中的错误数据。 通过对第一数据组中的错误数据和第二数据组中的错误数据进行校正，来重新写入存储器单元中的数据。 中央处理单元（CPU）可以检测第二数据组中的错误。 可以通过页缓冲器读取第二数据组，并与存储在SRAM中的第一数据组进行比较。 检测到的错误可能更新到页面缓冲区。 第一个数据组中的错误数据可能更新到页面缓冲区。 CPU更正最终错误数据中的错误，并且页缓冲区重写多个存储单元中的校正数据。

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