中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

214 records (took 0.026 seconds)

    Method for setting compensation region for irregular deffect region in manage display device
    71.
    发明申请
    Method for setting compensation region for irregular deffect region in manage display device 有权
    管理显示设备中不规则影响区域的补偿区域设置方法

    公开(公告)号：US20100053204A1

    公开(公告)日：2010-03-04

    申请号：US12318267

    申请日：2008-12-23

    Applicant: Jong Hee Hwang ,  Hye Jin Kim ,  Ju Seong Park

    Inventor： Jong Hee Hwang ,  Hye Jin Kim ,  Ju Seong Park

    IPC: G09G5/00

    CPC classification number: G09G3/3648 ,  G09G3/006 ,  G09G2320/0233 ,  G09G2320/0285

    Abstract: The present invention relates to a method for setting a compensation region for an irregular defect region in an image display device, including the steps of detecting an irregular display defect, setting a horizontal width of the irregular defect region detected thus, generating a plurality of guide lines which divide the irregular defect region in a horizontal direction along the horizontal width set thus automatically, setting upper and lower side boundary lines to the irregular defect region at every interval of the plurality of the guide lines to generate a plurality of main compensation regions defined by the plurality of guide lines and the upper and lower side boundary lines, and generating a plurality of upper, lower, left, and right supplementary compensation regions at upper, lower, left, and right sides of the plurality of main compensation regions, which maintain a gap of each of the plurality of the guide lines, automatically.

    Abstract translation: 本发明涉及一种用于设置图像显示装置中的不规则缺陷区域的补偿区域的方法，包括以下步骤：检测不规则显示缺陷，设置由此检测到的不规则缺陷区域的水平宽度，产生多个引导件 沿着自动设定的水平宽度在水平方向上划分不规则缺陷区域的线条，将多个引导线的每个间隔的上下边界线设置到不规则缺陷区域，以生成多个主要补偿区域 通过多根引导线和上下侧边界线，并且在多个主补偿区域的上，下，左，右侧产生多个上，下，左和右补充补偿区域，其中 自动地保持多条引导线中的每一条的间隙。

    User authentication system and method thereof
    72.
    发明授权
    User authentication system and method thereof 有权
    用户认证系统及其方法

    公开(公告)号：US07634113B2

    公开(公告)日：2009-12-15

    申请号：US11291607

    申请日：2005-11-30

    Applicant: Do-Hyung Kim ,  Jae-Yeon Lee ,  Su-Young Chi ,  Ho-Sub Yoon ,  Kye-Kyung Kim ,  Soo-Hyun Cho ,  Hye-Jin Kim ,  Young-Jo Cho

    Inventor： Do-Hyung Kim ,  Jae-Yeon Lee ,  Su-Young Chi ,  Ho-Sub Yoon ,  Kye-Kyung Kim ,  Soo-Hyun Cho ,  Hye-Jin Kim ,  Young-Jo Cho

    IPC: G06K9/00 ,  G06K5/00 ,  G05B19/00 ,  G10L21/00

    CPC classification number: G06K9/00362

    Abstract: A user recognizing system and method is provided. According to the user recognizing system and method, user ID and predetermined user feature information are stored, first and second user feature information are extracted from the user image data transmitted from the image input unit, and first and second probabilities that the extracted first and second user feature information determine the predetermined user are respectively generated based on the information stored at the user information database, the first user feature information being absolutely unique biometric information and the second user feature information being unique semibiometric information under a predetermined condition, and ID of the input image is finally determined by combining the first probability and the second probability. According to the user recognizing system and method, a user identity can be authenticated even when the user freely moves.

    Abstract translation: 提供了一种用户识别系统和方法。 根据用户识别系统和方法，存储用户ID和预定用户特征信息，从从图像输入单元发送的用户图像数据中提取第一和第二用户特征信息，以及提取的第一和第二概率的第一和第二概率 基于存储在用户信息数据库中的信息分别生成预定用户的用户特征信息，第一用户特征信息是绝对唯一的生物体信息，第二用户特征信息是预定条件下的唯一半身测量信息，以及ID 最终通过组合第一概率和第二概率来确定输入图像。 根据用户识别系统和方法，即使用户自由移动，也可以认证用户身份。

    Semiconductor device and semiconductor system having the same
    73.
    发明申请
    Semiconductor device and semiconductor system having the same 有权
    半导体器件和具有该半导体器件的半导体系统

    公开(公告)号：US20090303807A1

    公开(公告)日：2009-12-10

    申请号：US12453872

    申请日：2009-05-26

    Applicant: Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

    Inventor： Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

    IPC: G11C7/00 ,  G11C11/00

    CPC classification number: G11C13/0069 ,  G11C7/22 ,  G11C8/12 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2207/2209

    Abstract: A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.

    Abstract translation: 根据示例实施例的半导体器件可以被配置为使得当执行写入操作时输入用于执行读取操作的读取命令，并且当在写入操作期间由写入地址访问的存储体组与 存储体在读取操作期间由读取地址访问，半导体器件可以自动暂停写入操作或响应于内部信号直到读取操作完成，并且在读取操作完成之后执行写入操作。

    Non-Volatile memory device using variable resistance element with an improved write performance
    74.
    发明申请
    Non-Volatile memory device using variable resistance element with an improved write performance 有权
    使用可变电阻元件的非易失性存储器件具有改进的写入性能

    公开(公告)号：US20090154221A1

    公开(公告)日：2009-06-18

    申请号：US12314513

    申请日：2008-12-11

    Applicant: Hye-Jin Kim ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Hung-Jun An

    Inventor： Hye-Jin Kim ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Hung-Jun An

    IPC: G11C11/00 ,  G11C7/00 ,  G11C5/14

    CPC classification number: G11C7/1078 ,  G11C5/14 ,  G11C7/1096 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

    Abstract: A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator generating a first voltage, a voltage pad receiving an external voltage that has a level higher than the first voltage, a sense amplifier supplied with the first voltage and reading data from the non-volatile memory cells selected from the memory cell array, and a write driver supplied with the external voltage and writing data to the non-volatile memory cells selected from the memory cell array.

    Abstract translation: 提供了使用可变电阻元件的非易失性存储器件。 非易失性存储器件包括具有多个非易失性存储器单元的存储单元阵列，产生第一电压的第一电压发生器，接收高于第一电压的电平的外部电压的电压焊盘，读出放大器 提供第一电压并从存储单元阵列中选择的非易失性存储单元读取数据，以及提供有外部电压的写入驱动器，并将数据写入从存储单元阵列中选择的非易失性存储单元。

    Phase change memory device and associated wordline driving circuit
    75.
    发明授权
    Phase change memory device and associated wordline driving circuit 失效
    相变存储器件和相关的字线驱动电路

    公开(公告)号：US07548446B2

    公开(公告)日：2009-06-16

    申请号：US11319604

    申请日：2005-12-29

    Applicant: Hye-jin Kim ,  Du-eung Kim ,  Beak-hyung Cho ,  Hyung-rok Oh

    Inventor： Hye-jin Kim ,  Du-eung Kim ,  Beak-hyung Cho ,  Hyung-rok Oh

    IPC: G11C11/00

    CPC classification number: G11C13/0004 ,  G11C8/08 ,  G11C13/0028

    Abstract: A semiconductor memory device includes a plurality of wordline driving circuits adapted to control the voltage level of a sub-wordline in response to a logic state of a global wordline and an address signal. The wordline driving circuit comprises first and second transistors configured to maintain the sub-wordline at a first voltage level when the global wordline and the address signal have a first logic state and at a second voltage level when the global wordline or the address signal have a second logic state.

    Abstract translation: 半导体存储器件包括多个字线驱动电路，其适于响应于全局字线和地址信号的逻辑状态来控制子字线的电压电平。 字线驱动电路包括第一和第二晶体管，其被配置为当全局字线和地址信号具有第一逻辑状态并且当全局字线或地址信号具有第一电压电平时，将子字线保持在第一电压电平 第二逻辑状态。

    NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE MATERIALS
    77.
    发明申请
    NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE MATERIALS 审中-公开
    使用可变电阻材料的非易失性存储器件

    公开(公告)号：US20080291715A1

    公开(公告)日：2008-11-27

    申请号：US12116295

    申请日：2008-05-07

    Applicant: Mu-Hui PARK ,  Kwang-Jin LEE ,  Du-Eung KIM ,  Hye-Jin KIM ,  Woo-Yeong CHO

    Inventor： Mu-Hui PARK ,  Kwang-Jin LEE ,  Du-Eung KIM ,  Hye-Jin KIM ,  Woo-Yeong CHO

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C13/0038 ,  G11C7/04 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028

    Abstract: A nonvolatile memory device includes a nonvolatile memory cell, a read circuit and a control bias generating circuit. The nonvolatile memory cell has a resistance level that changes depending on stored data. The read circuit reads the resistance level of the nonvolatile memory cell by receiving a control bias and supplying the nonvolatile memory cell a read bias based on the control bias. The control bias generating circuit receives an input bias, generates the control bias based on the input bias and supplies the control bias to the read circuit. A slope of the control bias to the input bias is less than 1.

    Abstract translation: 非易失性存储器件包括非易失性存储单元，读取电路和控制偏置产生电路。 非易失性存储单元具有根据存储的数据而改变的电阻水平。 读取电路通过接收控制偏置来读取非易失性存储单元的电阻电平，并且基于控制偏压向非易失性存储单元提供读取偏置。 控制偏置产生电路接收输入偏置，基于输入偏置产生控制偏压，并将控制偏压提供给读取电路。 对输入偏置的控制偏置的斜率小于1。

    BIAS VOLTAGE GENERATOR AND METHOD GENERATING BIAS VOLTAGE FOR SEMICONDUCTOR MEMORY DEVICE
    79.
    发明申请
    BIAS VOLTAGE GENERATOR AND METHOD GENERATING BIAS VOLTAGE FOR SEMICONDUCTOR MEMORY DEVICE 有权
    偏置电压发生器和生成半导体存储器件的偏置电压的方法

    公开(公告)号：US20080159017A1

    公开(公告)日：2008-07-03

    申请号：US11955562

    申请日：2007-12-13

    Applicant: Hye-Jin KIM ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Mu-Hui PARK

    Inventor： Hye-Jin KIM ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Mu-Hui PARK

    IPC: G11C5/14

    CPC classification number: G11C13/004 ,  G11C5/147 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C16/30 ,  G11C2013/0054 ,  G11C2213/72

    Abstract: There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that the bias voltage is output in response to an input voltage being applied, so that a slope of the bias voltage to the input voltage is different in at least two sections divided corresponding to a level of the input voltage.

    Abstract translation: 提供了偏置电压发生器，具有偏置电压发生器的半导体存储器件以及用于产生偏置电压的方法。 产生用于控制提供给存储单元的感测电流以感测数据的偏置电压的偏置电压发生器的特征在于，响应于所施加的输入电压而输出偏置电压，使得偏置电压的斜率 至少两个部分的输入电压不同，对应于输入电压的电平。

    Semiconductor memory device and core layout thereof
    80.
    发明授权
    Semiconductor memory device and core layout thereof 失效
    半导体存储器件及其核心布局

    公开(公告)号：US07391669B2

    公开(公告)日：2008-06-24

    申请号：US11316878

    申请日：2005-12-27

    Applicant: Hye-jin Kim ,  Choong-keun Kwak ,  Woo-yeong Cho ,  Sang-beom Kang

    Inventor： Hye-jin Kim ,  Choong-keun Kwak ,  Woo-yeong Cho ,  Sang-beom Kang

    IPC: G11C8/00

    CPC classification number: G11C13/0028 ,  G11C13/0004

    Abstract: A semiconductor memory device of one aspect includes a memory cell block including n global word lines, and corresponding m sub word lines for each of the n global word lines, where n and m are natural numbers. The memory device further includes a plurality of word line driving circuits which respectively control a voltage of the sub word lines according to a logic level of each corresponding global word line and inputted address signals, and a plurality of control circuits which transmit the address signals to the word line driving circuits or interrupt transmission of the address signals according to the logic level of the global word line. Each of the word line driving circuits includes a first transistor which maintains the voltage of the respective sub word line at a first voltage and a second transistor which maintains the voltage of the sub word line at the first voltage or a second voltage.

    Abstract translation: 一个方面的半导体存储器件包括包括n个全局字线的存储单元块，以及n个全局字线中的每一个的对应m个子字线，其中n和m是自然数。 存储装置还包括多个字线驱动电路，其分别根据每个对应的全局字线和输入的地址信号的逻辑电平分别控制子字线的电压，以及多个控制电路，其将地址信号发送到 字线驱动电路或根据全局字线的逻辑电平中断地址信号的传输。 每个字线驱动电路包括将相应子字线的电压维持在第一电压的第一晶体管和将子字线的电压维持在第一电压或第二电压的第二晶体管。

Patent Agency Ranking