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    Semiconductor memory device and core layout thereof
    1.
    发明申请
    Semiconductor memory device and core layout thereof 失效
    半导体存储器件及其核心布局

    公开(公告)号：US20060215480A1

    公开(公告)日：2006-09-28

    申请号：US11316878

    申请日：2005-12-27

    申请人： Hye-jin Kim ,  Choong-keun Kwak ,  Woo-yeong Cho ,  Sang-beom Kang

    发明人： Hye-jin Kim ,  Choong-keun Kwak ,  Woo-yeong Cho ,  Sang-beom Kang

    IPC分类号： G11C8/00

    CPC分类号： G11C13/0028 ,  G11C13/0004

    摘要： A semiconductor memory device of one aspect includes a memory cell block including n global word lines, and corresponding m sub word lines for each of the n global word lines, where n and m are natural numbers. The memory device further includes a plurality of word line driving circuits which respectively control a voltage of the sub word lines according to a logic level of each corresponding global word line and inputted address signals, and a plurality of control circuits which transmit the address signals to the word line driving circuits or interrupt transmission of the address signals according to the logic level of the global word line. Each of the word line driving circuits includes a first transistor which maintains the voltage of the respective sub word line at a first voltage and a second transistor which maintains the voltage of the sub word line at the first voltage or a second voltage.

    摘要翻译： 一个方面的半导体存储器件包括包括n个全局字线的存储单元块，以及n个全局字线中的每一个的对应m个子字线，其中n和m是自然数。 存储装置还包括多个字线驱动电路，其分别根据每个对应的全局字线和输入的地址信号的逻辑电平分别控制子字线的电压，以及多个控制电路，其将地址信号发送到 字线驱动电路或根据全局字线的逻辑电平中断地址信号的传输。 每个字线驱动电路包括将相应子字线的电压维持在第一电压的第一晶体管和将子字线的电压维持在第一电压或第二电压的第二晶体管。

    Semiconductor memory device and core layout thereof
    2.
    发明授权
    Semiconductor memory device and core layout thereof 失效
    半导体存储器件及其核心布局

    公开(公告)号：US07391669B2

    公开(公告)日：2008-06-24

    申请号：US11316878

    申请日：2005-12-27

    申请人： Hye-jin Kim ,  Choong-keun Kwak ,  Woo-yeong Cho ,  Sang-beom Kang

    发明人： Hye-jin Kim ,  Choong-keun Kwak ,  Woo-yeong Cho ,  Sang-beom Kang

    IPC分类号： G11C8/00

    CPC分类号： G11C13/0028 ,  G11C13/0004

    摘要： A semiconductor memory device of one aspect includes a memory cell block including n global word lines, and corresponding m sub word lines for each of the n global word lines, where n and m are natural numbers. The memory device further includes a plurality of word line driving circuits which respectively control a voltage of the sub word lines according to a logic level of each corresponding global word line and inputted address signals, and a plurality of control circuits which transmit the address signals to the word line driving circuits or interrupt transmission of the address signals according to the logic level of the global word line. Each of the word line driving circuits includes a first transistor which maintains the voltage of the respective sub word line at a first voltage and a second transistor which maintains the voltage of the sub word line at the first voltage or a second voltage.

    摘要翻译： 一个方面的半导体存储器件包括包括n个全局字线的存储单元块，以及n个全局字线中的每一个的对应m个子字线，其中n和m是自然数。 存储装置还包括多个字线驱动电路，其分别根据每个对应的全局字线和输入的地址信号的逻辑电平分别控制子字线的电压，以及多个控制电路，其将地址信号发送到 字线驱动电路或根据全局字线的逻辑电平中断地址信号的传输。 每个字线驱动电路包括将相应子字线的电压维持在第一电压的第一晶体管和将子字线的电压维持在第一电压或第二电压的第二晶体管。

    Method of programming a memory cell array using successive pulses of increased duration
    3.
    发明授权
    Method of programming a memory cell array using successive pulses of increased duration 有权
    使用增加的持续时间的连续脉冲对存储器单元阵列进行编程的方法

    公开(公告)号：US07515459B2

    公开(公告)日：2009-04-07

    申请号：US11315129

    申请日：2005-12-23

    申请人： Sang-beom Kang ,  Du-eung Kim ,  Beak-hyung Cho ,  Hye-jin Kim

    发明人： Sang-beom Kang ,  Du-eung Kim ,  Beak-hyung Cho ,  Hye-jin Kim

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

    摘要： A method of programming a memory array including a plurality of memory cells is provided. The memory cells may include phase-change memory elements. In one aspect, the method includes applying in succession first through nth current pulses to each of the memory cells to be programmed to a first state (e.g., a crystalline state), where a current amplitude of the first through nth current pulses decreases with each successive pulse, and where a pulse duration of the first through nth current pulses increases with each successive pulse.

    摘要翻译： 提供了一种编程包括多个存储单元的存储器阵列的方法。 存储器单元可以包括相变存储元件。 在一个方面，该方法包括将第一至第n电流脉冲连续地应用于要被编程到第一状态（例如，结晶状态）的每个存储器单元，其中第一至第n电流脉冲的电流幅度随着每个 连续脉冲，并且其中第一至第n电流脉冲的脉冲持续时间随着每个连续脉冲而增加。

    Method of programming memory cell array
    4.
    发明申请
    Method of programming memory cell array 有权
    编程存储单元阵列的方法

    公开(公告)号：US20060221679A1

    公开(公告)日：2006-10-05

    申请号：US11315129

    申请日：2005-12-23

    申请人： Sang-beom Kang ,  Du-eung Kim ,  Baek-hyung Cho ,  Hye-jin Kim

    发明人： Sang-beom Kang ,  Du-eung Kim ,  Baek-hyung Cho ,  Hye-jin Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

    摘要： A method of programming a memory array including a plurality of memory cells is provided. The memory cells may include phase-change memory elements. In one aspect, the method includes applying in succession first through nth current pulses to each of the memory cells to be programmed to a first state (e.g., a crystalline state), where a current amplitude of the first through nth current pulses decreases with each successive pulse, and where a pulse duration of the first through nth current pulses increases with each successive pulse.

    摘要翻译： 提供了一种编程包括多个存储单元的存储器阵列的方法。 存储器单元可以包括相变存储元件。 在一个方面，所述方法包括首先连续地将每个存储单元连续施加到要编程到第一状态（例如，结晶状态）的第n个/ 第一至第n个电流脉冲随着每个连续脉冲而减小，并且其中第一至第n个电流脉冲的脉冲持续时间随每个连续脉冲而增加。

    Non-volatile phase-change memory device and associated program-suspend-read operation
    7.
    发明授权
    Non-volatile phase-change memory device and associated program-suspend-read operation 有权
    非易失性相变存储器件和相关的程序挂起读操作

    公开(公告)号：US07349245B2

    公开(公告)日：2008-03-25

    申请号：US11486100

    申请日：2006-07-14

    申请人： Hye-jin Kim ,  Kwang-jin Lee ,  Sang-Beom Kang ,  Mu-hui Park

    发明人： Hye-jin Kim ,  Kwang-jin Lee ,  Sang-Beom Kang ,  Mu-hui Park

    IPC分类号： G11C11/00 ,  G11C11/14

    CPC分类号： G11C8/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078

    摘要： A method of performing a program-suspend-read operation in a PRAM device comprises programming a write block comprising N unit program blocks in response to a program operation request, and suspending the program operation after programming M unit program blocks, where M is less than N, in response to a read operation request. The method further comprises executing the requested read operation, and then resuming the programming of the write data block and programming (N−M) remaining unit program blocks.

    摘要翻译： 一种在PRAM设备中执行程序挂起读取操作的方法包括响应于程序操作请求编程包含N个单元程序块的写入块，并且在对M个单元程序块进行编程之后暂停编程操作，其中M小于 N，响应于读取操作请求。 该方法还包括执行所请求的读取操作，然后恢复写入数据块和编程（N-M）剩余单元程序块的编程。

    Non-volatile phase-change memory device and associated program-suspend-read operation
    9.
    发明申请
    Non-volatile phase-change memory device and associated program-suspend-read operation 有权
    非易失性相变存储器件和相关的程序挂起读操作

    公开(公告)号：US20070217253A1

    公开(公告)日：2007-09-20

    申请号：US11486100

    申请日：2006-07-14

    申请人： Hye-jin Kim ,  Kwang-jin Lee ,  Sang-Beom Kang ,  Mu-hui Park

    发明人： Hye-jin Kim ,  Kwang-jin Lee ,  Sang-Beom Kang ,  Mu-hui Park

    IPC分类号： G11C11/00

    CPC分类号： G11C8/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078

    摘要： A method of performing a program-suspend-read operation in a PRAM device comprises programming a write block comprising N unit program blocks in response to a program operation request, and suspending the program operation after programming M unit program blocks, where M is less than N, in response to a read operation request. The method further comprises executing the requested read operation, and then resuming the programming of the write data block and programming (N−M) remaining unit program blocks.

    摘要翻译： 一种在PRAM设备中执行程序挂起读取操作的方法包括响应于程序操作请求编程包含N个单元程序块的写入块，并且在对M个单元程序块进行编程之后暂停编程操作，其中M小于 N，响应于读取操作请求。 该方法还包括执行所请求的读取操作，然后恢复写入数据块和编程（N-M）剩余单元程序块的编程。

    Digital image processing apparatus and method for simultaneously displaying input image and setting information on display screen
    10.
    发明授权
    Digital image processing apparatus and method for simultaneously displaying input image and setting information on display screen 有权
    数字图像处理装置和方法，用于在显示屏幕上同时显示输入图像和设置信息

    公开(公告)号：US08988577B2

    公开(公告)日：2015-03-24

    申请号：US12979548

    申请日：2010-12-28

    申请人： Se-hyun Park ,  Jung-ah Heo ,  Hyo-sang Bang ,  Hye-jin Kim

    发明人： Se-hyun Park ,  Jung-ah Heo ,  Hyo-sang Bang ,  Hye-jin Kim

    IPC分类号： H04N5/222 ,  H04N5/232

    CPC分类号： H04N5/23293 ,  H04N5/232

    摘要： A digital image processing apparatus, which displays a setting item designated by a user together with a setting status of a setting value for the setting item to allow the user to efficiently set items necessary for photographing and/or other operations, and a control method for the apparatus. The apparatus includes: a body; and a display unit on the body where setting information is displayed, wherein a display screen displayed on the display unit includes: a selection region where at least one setting item is displayed; and an adjustment region where a currently set current setting value is displayed together with candidate setting values that can be set for at least one of the at least one setting item.

    摘要翻译： 一种数字图像处理装置，其显示由用户指定的设置项目以及设置项目的设置值的设置状态，以允许用户有效地设置拍摄和/或其他操作所需的项目，以及控制方法 该装置。 该装置包括：身体; 以及在主体上的显示设置信息的显示单元，其中显示在显示单元上的显示屏幕包括：显示至少一个设置项目的选择区域; 以及显示当前设定的当前设定值的调整区域以及可以对至少一个设定项目中的至少一个设定的候选设定值。