公开(公告)号：US07391669B2

公开(公告)日：2008-06-24

申请号：US11316878

申请日：2005-12-27

申请人： Hye-jin Kim ,  Choong-keun Kwak ,  Woo-yeong Cho ,  Sang-beom Kang

发明人： Hye-jin Kim ,  Choong-keun Kwak ,  Woo-yeong Cho ,  Sang-beom Kang

IPC分类号： G11C8/00

CPC分类号： G11C13/0028 ,  G11C13/0004

摘要： A semiconductor memory device of one aspect includes a memory cell block including n global word lines, and corresponding m sub word lines for each of the n global word lines, where n and m are natural numbers. The memory device further includes a plurality of word line driving circuits which respectively control a voltage of the sub word lines according to a logic level of each corresponding global word line and inputted address signals, and a plurality of control circuits which transmit the address signals to the word line driving circuits or interrupt transmission of the address signals according to the logic level of the global word line. Each of the word line driving circuits includes a first transistor which maintains the voltage of the respective sub word line at a first voltage and a second transistor which maintains the voltage of the sub word line at the first voltage or a second voltage.

摘要翻译： 一个方面的半导体存储器件包括包括n个全局字线的存储单元块，以及n个全局字线中的每一个的对应m个子字线，其中n和m是自然数。 存储装置还包括多个字线驱动电路，其分别根据每个对应的全局字线和输入的地址信号的逻辑电平分别控制子字线的电压，以及多个控制电路，其将地址信号发送到 字线驱动电路或根据全局字线的逻辑电平中断地址信号的传输。 每个字线驱动电路包括将相应子字线的电压维持在第一电压的第一晶体管和将子字线的电压维持在第一电压或第二电压的第二晶体管。

公开(公告)号：US20060215480A1

公开(公告)日：2006-09-28

申请号：US11316878

申请日：2005-12-27

申请人： Hye-jin Kim ,  Choong-keun Kwak ,  Woo-yeong Cho ,  Sang-beom Kang

发明人： Hye-jin Kim ,  Choong-keun Kwak ,  Woo-yeong Cho ,  Sang-beom Kang

IPC分类号： G11C8/00

CPC分类号： G11C13/0028 ,  G11C13/0004

摘要： A semiconductor memory device of one aspect includes a memory cell block including n global word lines, and corresponding m sub word lines for each of the n global word lines, where n and m are natural numbers. The memory device further includes a plurality of word line driving circuits which respectively control a voltage of the sub word lines according to a logic level of each corresponding global word line and inputted address signals, and a plurality of control circuits which transmit the address signals to the word line driving circuits or interrupt transmission of the address signals according to the logic level of the global word line. Each of the word line driving circuits includes a first transistor which maintains the voltage of the respective sub word line at a first voltage and a second transistor which maintains the voltage of the sub word line at the first voltage or a second voltage.

摘要翻译： 一个方面的半导体存储器件包括包括n个全局字线的存储单元块，以及n个全局字线中的每一个的对应m个子字线，其中n和m是自然数。 存储装置还包括多个字线驱动电路，其分别根据每个对应的全局字线和输入的地址信号的逻辑电平分别控制子字线的电压，以及多个控制电路，其将地址信号发送到 字线驱动电路或根据全局字线的逻辑电平中断地址信号的传输。 每个字线驱动电路包括将相应子字线的电压维持在第一电压的第一晶体管和将子字线的电压维持在第一电压或第二电压的第二晶体管。

公开(公告)号：US07457151B2

公开(公告)日：2008-11-25

申请号：US11319601

申请日：2005-12-29

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang ,  Choong-keun Kwak

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang ,  Choong-keun Kwak

IPC分类号： G11C11/00

CPC分类号： G11C13/0038 ,  G11C5/145 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/009

摘要： A phase change memory device of one aspect includes a memory array including a plurality of phase change memory cells, a write boosting circuit, and a write driver. The write boosting circuit boosts a first voltage and outputs a first control voltage in response to a control signal in a first operation mode, and boosts the first voltage and outputs a second control voltage in response to the control signal in a second operation mode and a third operation mode. The write driver is driven by the first control voltage in the first operation mode and writes data to a selected memory cell of the memory array.

摘要翻译： 一个方面的相变存储器件包括包括多个相变存储单元，写升压电路和写驱动器的存储器阵列。 写升压电路响应于第一操作模式中的控制信号而升高第一电压并输出第一控制电压，并且在第二操作模式中响应于控制信号升高第一电压并输出第二控制电压，并且 第三操作模式。 写入驱动器由第一操作模式中的第一控制电压驱动，并将数据写入存储器阵列的所选存储单元。

公开(公告)号：US20070014150A1

公开(公告)日：2007-01-18

申请号：US11319601

申请日：2005-12-29

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang ,  Choong-keun Kwak

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang ,  Choong-keun Kwak

IPC分类号： G11C11/00 ,  G11C8/00

CPC分类号： G11C13/0038 ,  G11C5/145 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/009

摘要： A phase change memory device of one aspect includes a memory array including a plurality of phase change memory cells, a write boosting circuit, and a write driver. The write boosting circuit boosts a first voltage and outputs a first control voltage in response to a control signal in a first operation mode, and boosts the first voltage and outputs a second control voltage in response to the control signal in a second operation mode and a third operation mode. The write driver is driven by the first control voltage in the first operation mode and writes data to a selected memory cell of the memory array.

摘要翻译： 一个方面的相变存储器件包括包括多个相变存储单元，写升压电路和写驱动器的存储器阵列。 写升压电路升压第一电压并响应于第一操作模式中的控制信号输出第一控制电压，并且在第二操作模式中响应于控制信号升高第一电压并输出第二控制电压，并且 第三操作模式。 写入驱动器由第一操作模式中的第一控制电压驱动，并将数据写入存储器阵列的所选存储单元。

公开(公告)号：US07283387B2

公开(公告)日：2007-10-16

申请号：US11316256

申请日：2005-12-23

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

IPC分类号： G11C11/00 ,  G11C5/14

CPC分类号： G11C13/0038 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

摘要： A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines, and a control node connecting the data lines to a sense amplifier unit. In a write operation mode, control voltages obtained by boosting a first voltage are respectively applied to the control node and gates of the column selection transistors, and a ground voltage is applied to a word line of a selected one of the phase change memory cells. In a standby mode, word lines and bit lines connected to the phase change memory cells of the memory array are maintained at the same voltage. According to the phase change memory device and a driving method thereof, a sufficient write voltage is supplied to a write driver, a column decoder and a row decoder in the write operation mode, and a voltage lower is applied to the write driver, the column decoder and the row decoder in the read operation mode and the standby mode, thereby reducing current consumption and enhancing operational reliability.

摘要翻译： 相变存储器件包括包括多个相变存储器单元的存储器阵列，每个相变存储单元包括相变材料和二极管，多个列选择晶体管将连接到相变存储单元的位线连接到相应的 数据线和将数据线连接到读出放大器单元的控制节点。 在写入操作模式中，通过升压第一电压获得的控制电压分别施加到列选择晶体管的控制节点和栅极，并且将接地电压施加到所选择的一个相变存储单元的字线。 在备用模式中，连接到存储器阵列的相变存储单元的字线和位线保持在相同的电压。 根据相变存储器件及其驱动方法，在写入操作模式中向写入驱动器，列解码器和行解码器提供足够的写入电压，并且将较低的电压施加到写入驱动器，列 解码器和行解码器处于读取操作模式和待机模式，从而降低电流消耗并提高操作可靠性。

公开(公告)号：US20070058425A1

公开(公告)日：2007-03-15

申请号：US11316256

申请日：2005-12-23

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

IPC分类号： G11C11/00

CPC分类号： G11C13/0038 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

摘要： A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines, and a control node connecting the data lines to a sense amplifier unit. In a write operation mode, control voltages obtained by boosting a first voltage are respectively applied to the control node and gates of the column selection transistors, and a ground voltage is applied to a word line of a selected one of the phase change memory cells. In a standby mode, word lines and bit lines connected to the phase change memory cells of the memory array are maintained at the same voltage. According to the phase change memory device and a driving method thereof, a sufficient write voltage is supplied to a write driver, a column decoder and a row decoder in the write operation mode, and a voltage lower is applied to the write driver, the column decoder and the row decoder in the read operation mode and the standby mode, thereby reducing current consumption and enhancing operational reliability.

公开(公告)号：US20060215440A1

公开(公告)日：2006-09-28

申请号：US11348432

申请日：2006-02-06

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C11/5678 ,  G11C13/0004

摘要： Phase-changeable random access memory (PRAM) devices include a plurality of rows and columns of PRAM memory cells therein and at least one local bit line electrically coupled to a column of the PRAM memory cells. First and second bit line selection circuits are provided to increase the rate at which the at least one local bit line can be accessed and driven with a bit line signal. These first and second bit line selection circuits are configured to electrically connect first and second ends of the at least one local bit line to a global bit line during an operation to read data from a selected one of the PRAM memory cells in the column.

摘要翻译： 相位可变随机存取存储器（PRAM）装置包括其中的多个行和列的PRAM存储器单元，以及电耦合到PRAM存储器单元的列的至少一个局部位线。 提供第一和第二位线选择电路以增加利用位线信号来访问和驱动至少一个局部位线的速率。 这些第一位线选择电路和第二位线选择电路被配置为在操作期间将至少一个局部位线的第一和第二端电连接到全局位线，以从列中的所选PRAM存储器单元读取数据。

公开(公告)号：US07397681B2

公开(公告)日：2008-07-08

申请号：US11348432

申请日：2006-02-06

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

IPC分类号： G11C27/00

CPC分类号： G11C11/5678 ,  G11C13/0004

摘要： Phase-changeable random access memory (PRAM) devices include a plurality of rows and columns of PRAM memory cells therein and at least one local bit line electrically coupled to a column of the PRAM memory cells. First and second bit line selection circuits are provided to increase the rate at which the at least one local bit line can be accessed and driven with a bit line signal. These first and second bit line selection circuits are configured to electrically connect first and second ends of the at least one local bit line to a global bit line during an operation to read data from a selected one of the PRAM memory cells in the column.

摘要翻译： 相位可变随机存取存储器（PRAM）装置包括其中的多个行和列的PRAM存储器单元，以及电耦合到PRAM存储器单元的列的至少一个局部位线。 提供第一和第二位线选择电路以增加利用位线信号来访问和驱动至少一个局部位线的速率。 这些第一位线选择电路和第二位线选择电路被配置为在操作期间将至少一个局部位线的第一和第二端电连接到全局位线，以从列中的所选PRAM存储器单元读取数据。

公开(公告)号：US07859882B2

公开(公告)日：2010-12-28

申请号：US11844511

申请日：2007-08-24

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang

IPC分类号： G11C11/00

CPC分类号： G11C8/14 ,  G11C13/00 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2213/79

摘要： A resistive memory device is provided. The resistive memory device includes word lines arranged in M rows, bit lines arranged in N columns, local source lines arranged in M/2 rows, and resistive memory cells arranged in M rows and N columns. Each of the resistive memory cells includes a resistance variable element having a first electrode connected to a corresponding bit line, and a cell transistor having a first terminal connected to a second electrode of the resistance variable element, a second terminal connected to a corresponding local source line, and a control terminal connected to a corresponding word line. The local source line is commonly connected to the second terminals of the cell transistors of the two neighboring rows.

摘要翻译： 提供了一种电阻式存储器件。 电阻式存储装置包括排列成M行的字线，以N列排列的位线，以M / 2行排列的局部源极线以及布置成M行N列的电阻存储单元。 每个电阻存储单元包括电阻可变元件，电阻可变元件具有连接到对应的位线的第一电极，以及单元晶体管，其具有连接到电阻可变元件的第二电极的第一端子，连接到相应的本地源极的第二端子 线路和连接到相应字线的控制终端。 本地源极线通常连接到两个相邻行的单元晶体管的第二端子。

公开(公告)号：US07843716B2

公开(公告)日：2010-11-30

申请号：US12031085

申请日：2008-02-14

申请人： Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Joon-min Park

发明人： Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Joon-min Park

IPC分类号： G11C5/02

CPC分类号： G11C7/067 ,  G11C5/025 ,  G11C5/04 ,  G11C7/062 ,  G11C8/10 ,  G11C8/14 ,  G11C11/16 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2207/063 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile memory device includes a stack-type memory cell array, a selection circuit and a read circuit. The memory cell array includes multiple memory cell layers and a reference cell layer, which are vertically laminated. Each of the memory cell layers includes multiple nonvolatile memory cells for storing data, and the reference cell layer includes multiple reference cells for storing reference data. The selection circuit selects a nonvolatile memory cell from the memory cell layers and at least one reference cell, corresponding to the selected nonvolatile memory cell, from the reference cell layer. The read circuit supplies a read bias to the selected nonvolatile memory cell and the selected reference cell corresponding to the selected nonvolatile memory cell, and reads data from the selected nonvolatile memory cell.

摘要翻译： 非易失性存储器件包括堆叠型存储单元阵列，选择电路和读取电路。 存储单元阵列包括垂直层叠的多个存储单元层和参考单元层。 每个存储单元层包括用于存储数据的多个非易失性存储单元，参考单元层包括用于存储参考数据的多个参考单元。 选择电路从参考单元层从存储单元层和对应于所选择的非易失性存储单元的至少一个参考单元选择非易失性存储单元。 读取电路向所选择的非易失性存储单元和与所选择的非易失性存储单元相对应的所选择的参考单元提供读偏置，并从所选择的非易失性存储单元读取数据。