公开(公告)号：US08442139B2

公开(公告)日：2013-05-14

申请号：US12543896

申请日：2009-08-19

Applicant: Joo-Hyun Lee ,  Jong-Ho Lee ,  Sung-Soo Hwang ,  Joon-Hyuk Kang ,  Won-Taek Song ,  Kyung-Ho Park ,  Nam-Seok Chang

Inventor： Joo-Hyun Lee ,  Jong-Ho Lee ,  Sung-Soo Hwang ,  Joon-Hyuk Kang ,  Won-Taek Song ,  Kyung-Ho Park ,  Nam-Seok Chang

IPC: H04B7/02 ,  H04L1/02

CPC classification number: H04B7/0639 ,  H04L25/0204 ,  H04L25/0228

Abstract: Apparatuses and methods for transmitting and receiving in a multi-antenna system are provided. A receiver for reducing a quantization error of channel information feedback in a multi-antenna system includes a restore vector generator for selecting a codeword ck and d determining a real part wkreal and an imaginary part wkimag of a restore vector corresponding to the codeword; and a post-processor for performing post-processing by multiplying the real part wkreal of the restore vector by a first reception signal and multiplying the imaginary part wkimag of the restore vector by a second reception signal.

Abstract translation: 提供了一种用于在多天线系统中发送和接收的装置和方法。 用于减少多天线系统中的信道信息反馈的量化误差的接收机包括用于选择码字ck的恢复向量生成器，以及确定与码字相对应的恢复向量的实部wkreal和虚部wkimag; 以及后处理器，用于通过将所述恢复向量的实部wkreal乘以第一接收信号并将所述恢复向量的虚部wkimag乘以第二接收信号来执行后处理。

公开(公告)号：US08367472B2

公开(公告)日：2013-02-05

申请号：US13070196

申请日：2011-03-23

Applicant: Jong Ho Lee ,  Dong Ho Lee ,  Eun Chul Ahn ,  Yong Chai Kwon

Inventor： Jong Ho Lee ,  Dong Ho Lee ,  Eun Chul Ahn ,  Yong Chai Kwon

IPC: H01L21/60

CPC classification number: H01L21/76898 ,  H01L23/525 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern.

Abstract translation: 一种制造半导体器件的方法包括提供具有活性表面的半导体衬底，通过从衬底的与活性表面相对的第二表面去除材料来稀释衬底，将金属载体接合到薄化衬底的第二表面上，形成 通过在所述薄化基板中的开口，在所述通孔开口中形成导电构件，并且图案化结合到所述薄化基板的第二表面的金属载体以形成金属图案。

公开(公告)号：US08315180B2

公开(公告)日：2012-11-20

申请号：US12475024

申请日：2009-05-29

Applicant: Jong-Ho Lee ,  Sang-Bo Yun ,  Sung-Hwan Kim ,  Sung-Yoon Jung ,  Nak-Myeong Kim ,  Su-Jung Shin ,  Hae-Lynn Kang ,  Hye-In Yu

Inventor： Jong-Ho Lee ,  Sang-Bo Yun ,  Sung-Hwan Kim ,  Sung-Yoon Jung ,  Nak-Myeong Kim ,  Su-Jung Shin ,  Hae-Lynn Kang ,  Hye-In Yu

IPC: G01R31/08 ,  H04W4/00

CPC classification number: H04B7/15557

Abstract: Method and apparatus for selecting an RS mode in a BWA communication system are provided. In a method for a BS to select an RS mode in a BWA communication system, bidding prices are received from a set of RSs covered by the BS. The winner RS of at least one or more auctions is determined on the basis of the bidding values and the interference information of the RS set. The winner RS is set to operate in an active mode.

Abstract translation: 提供了一种用于在BWA通信系统中选择RS模式的方法和装置。 在BS在BWA通信系统中选择RS模式的方法中，从BS覆盖的一组RS接收出价价格。 基于RS集的投标价值和干扰信息确定至少一个或多个拍卖的获胜者RS。 获胜者RS设置为以活动模式运行。

公开(公告)号：US08269238B2

公开(公告)日：2012-09-18

申请号：US12007495

申请日：2008-01-11

Applicant: Hyun Jun Kim ,  Chang Hwan Choi ,  Won Ha Moon ,  Jong Ho Lee ,  Jae Chul Yong ,  Jin Ha Kim

Inventor： Hyun Jun Kim ,  Chang Hwan Choi ,  Won Ha Moon ,  Jong Ho Lee ,  Jae Chul Yong ,  Jin Ha Kim

IPC: H01L33/00

CPC classification number: H01L33/20 ,  H01L33/46 ,  H01L33/502 ,  H01L33/508 ,  H01L2224/14 ,  H01L2933/0083

Abstract: A photonic crystal light emitting device including: a light emitting diode (LED) light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first and second conductive semiconductor layers; and a first photon-recycling light emitting layer formed on one surface of the first conductive semiconductor layer, opposite to the active layer, wherein the first photon-recycling light emitting layer absorbs a primary light emitted from the LED light emitting structure and emits a light having a different wavelength from that of the primary light, and a photonic crystal structure is formed on an entire thickness of the first photon-recycling light emitting layer.

Abstract translation: 1.一种光子晶体发光器件，包括：发光二极管（LED）发光结构，包括第一导电半导体层，第二导电半导体层和插入在所述第一和第二导电半导体层之间的有源层; 以及形成在与所述有源层相反的所述第一导电半导体层的一个表面上的第一光子再循环发光层，其中所述第一光子再循环发光层吸收从所述LED发光结构发射的初级光，并发射光 具有与初级光的波长不同的波长，并且在第一光子再循环发光层的整个厚度上形成光子晶体结构。

公开(公告)号：US20120223791A1

公开(公告)日：2012-09-06

申请号：US13172468

申请日：2011-06-29

Applicant: Ki Il KIM ,  Young K. KIM ,  Jong Ho LEE ,  Tae Wook KWON ,  Gui Hyeon MOON

Inventor： Ki Il KIM ,  Young K. KIM ,  Jong Ho LEE ,  Tae Wook KWON ,  Gui Hyeon MOON

IPC: H01F7/10

CPC classification number: G01G23/007 ,  G01G3/16

Abstract: Provided is a weight control system that can include: an upper plate positioned in a lower portion of the system; at least one of, a first magnet or a first electromagnet, configured to be concentrically engaged with the upper plate; an upper internal core; a coil; and an upper plate housing configured to receive the upper internal core and the coil, the upper plate housing being coupled to at least one of, the first magnet or the first electromagnet, wherein, when power is supplied to the system, an induced current is generated in the upper internal core and the coil to create a first centrifugal magnetic field configured to rotate the upper plate and at least one of, the first magnet or the first electromagnet.

Abstract translation: 提供了一种重量控制系统，其可以包括：位于系统的下部的上板; 第一磁体或第一电磁体中的至少一个，构造成与上板同心接合; 上部内部核心 线圈 以及上板壳体，其构造成容纳所述上内芯和所述线圈，所述上板壳体联接到所述第一磁体或所述第一电磁体中的至少一个，其中，当向所述系统供电时，感应电流为 在上内芯和线圈中产生以产生第一离心磁场，其被配置为旋转上板和第一磁体或第一电磁体中的至少一个。

公开(公告)号：US08208072B2

公开(公告)日：2012-06-26

申请号：US11496402

申请日：2006-08-01

Applicant: Jong-ho Lee ,  Kwang-kee Lee ,  Un-gyo Jung ,  Glenn A. Adams

Inventor： Jong-ho Lee ,  Kwang-kee Lee ,  Un-gyo Jung ,  Glenn A. Adams

IPC: H04N5/45

CPC classification number: G09G5/14 ,  G09G2340/0407 ,  G09G2340/0464 ,  G09G2340/10 ,  G09G2340/12 ,  G09G2340/125 ,  H04N5/445 ,  H04N5/44591 ,  H04N5/45 ,  H04N21/4312 ,  H04N21/4314 ,  H04N21/4316 ,  H04N21/443 ,  H04N21/4622

Abstract: An apparatus for providing multiple screens and a method of dynamically configuring multiple screens are provided. The apparatus for providing multiple screens includes a digital signal processing module which receives predetermined information and restores a service based on the predetermined information, a service processing module which displays one or more logical screens associated with the service, and an output module which arranges the logical screens provided by the service processing module at different locations on a display screen. The logical screens have attribute information indicating an order of displaying the logical screens that are mapped to the display screen.

Abstract translation: 提供了一种用于提供多个屏幕的装置和一种动态配置多个屏幕的方法。 用于提供多个屏幕的装置包括数字信号处理模块，其接收预定信息并基于预定信息恢复服务;服务处理模块，其显示与服务相关联的一个或多个逻辑屏幕;以及输出模块，其布置逻辑 由服务处理模块在显示屏幕上的不同位置提供的屏幕。 逻辑屏幕具有指示显示映射到显示屏幕的逻辑画面的顺序的属性信息。

公开(公告)号：US08143656B2

公开(公告)日：2012-03-27

申请号：US12200929

申请日：2008-08-28

Applicant: Jong-Ho Lee ,  Ki-Heung Park

Inventor： Jong-Ho Lee ,  Ki-Heung Park

IPC: H01L29/94

CPC classification number: H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

Abstract: Provided are a high-performance one-transistor floating-body DRAM cell device and a manufacturing method thereof. The one-transistor floating-body DRAM cell device includes: a semiconductor substrate; a gate stack which is formed on the semiconductor substrate; a control electrode which is formed on the semiconductor substrate and surrounded by the gate stack; a floating body which is formed on the control electrode that is surrounded by the gate stack; source/drain which are formed at left and right sides of the floating body; an insulating layer which insulates the source/drain from the semiconductor substrate and the control electrode; a gate insulating layer which is formed on the floating body and the source/drain; and a gate electrode which is formed on the gate insulating layer. In the cell device having a double-gate structure, charges can be stored in a non-volatile manner by the control electrodes, so that it is possible to improve a degree of integration of devices, a uniformity of characteristic, and a sensing margin.

Abstract translation: 提供一种高性能单晶体体浮体DRAM单元装置及其制造方法。 单晶体体浮体DRAM单元装置包括：半导体基板; 形成在所述半导体基板上的栅极叠层; 控制电极，其形成在所述半导体基板上并被所述栅极堆叠包围; 浮动体，其形成在所述控制电极上，所述浮体被所述栅极叠层包围; 在浮体的左侧和右侧形成的源极/漏极; 绝缘层，其使源极/漏极与半导体衬底和控制电极绝缘; 形成在浮体和源极/漏极上的栅极绝缘层; 以及形成在栅极绝缘层上的栅电极。 在具有双栅极结构的电池装置中，可以通过控制电极以非易失性的方式存储电荷，使得可以提高器件的集成度，特性的均匀性和感测裕度。

公开(公告)号：US08115262B2

公开(公告)日：2012-02-14

申请号：US12498311

申请日：2009-07-06

Applicant: Jong-Pyo Kim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Jung-Hyoung Lee

Inventor： Jong-Pyo Kim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Jung-Hyoung Lee

IPC: H01L21/02

CPC classification number: H01L21/28202 ,  H01L21/28185 ,  H01L21/28194 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/94 ,  Y10T428/265

Abstract: A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M1-xSixOy) or amorphous silicate nitride (M1-xSixOyNz), and an upper dielectric layer which is formed on top of the lower dielectric layer and which is made of amorphous metal oxide (M′Oy) or amorphous metal oxynitride (M′OyNz).

Abstract translation: 在一个实施例中提供了一种微电子器件的电介质多层结构，其中泄漏电流特性和介电常数得到改善。 电介质多层结构包括由非晶硅酸盐（M1-xSixOy）或无定形硅酸盐氮化物（M1-xSixOyNz）制成的下电介质层，以及形成在下电介质层的顶部上的上电介质层 的无定形金属氧化物（M'Oy）或无定形金属氧氮化物（M'OyNz）。

公开(公告)号：US08080480B2

公开(公告)日：2011-12-20

申请号：US12239122

申请日：2008-09-26

Applicant: Jong Ho Lee ,  Moo Youn Park ,  Soo Ryong Hwang ,  Il Hyung Jung ,  Gwan Su Lee ,  Jin Ha Kim

Inventor： Jong Ho Lee ,  Moo Youn Park ,  Soo Ryong Hwang ,  Il Hyung Jung ,  Gwan Su Lee ,  Jin Ha Kim

IPC: H01L21/302

CPC classification number: H01L33/20 ,  H01L21/30617 ,  H01L21/30621 ,  H01L21/3083 ,  H01L33/22 ,  H01L33/382

Abstract: A method of forming a fine pattern begins with providing a c-plane hexagonal semiconductor crystal. A mask having a predetermined pattern is formed on the semiconductor crystal. The semiconductor crystal is dry-etched by using the mask to form a first fine pattern on the semiconductor crystal. The semiconductor crystal including the first fine pattern is wet-etched to expand the first fine pattern in a horizontal direction to form a second fine pattern. The second fine pattern obtained in the wet-etching the semiconductor crystal has a bottom surface and a sidewall that have unique crystal planes, respectively. The present fine-pattern forming process can be advantageously applied to a semiconductor light emitting device, particularly, to a phonic crystal structure required to have fine patterns or a structure using a surface plasmon resonance principle.

Abstract translation: 形成精细图案的方法开始于提供c面六边形半导体晶体。 在半导体晶体上形成具有预定图案的掩模。 通过使用掩模对半导体晶体进行干蚀刻以在半导体晶体上形成第一精细图案。 包括第一精细图案的半导体晶体被湿蚀刻以在第一精细图案沿水平方向扩展以形成第二精细图案。 在半导体晶体的湿式蚀刻中获得的第二精细图案分别具有独特的晶面的底面和侧壁。 本发明的精细图案形成方法可以有利地应用于半导体发光器件，特别是应用于具有精细图案所需的语音晶体结构或使用表面等离子体共振原理的结构。

公开(公告)号：US20110287622A1

公开(公告)日：2011-11-24

申请号：US13195935

申请日：2011-08-02

Applicant: Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

Inventor： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

IPC: H01L21/28

CPC classification number: H01L21/28185 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

Abstract: Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

Abstract translation: 提供了在通道区​​域上包括多层电介质膜的晶体管。 多层电介质包括下电介质膜，该电介质膜的厚度至少为多层电介质膜的厚度的50％，并且包括金属氧化物，金属硅酸盐，铝酸盐或其混合物，以及上电介质膜 在下介电膜上，上电介质膜包含III族金属氧化物，III族金属氮化物，第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。 在多层电介质膜上设置栅电极。