公开(公告)号：US07768307B2

公开(公告)日：2010-08-03

申请号：US12005443

申请日：2007-12-26

Applicant: Kyung-Hoon Kim ,  Dae-Han Kwon

Inventor： Kyung-Hoon Kim ,  Dae-Han Kwon

IPC: H03K19/0175

CPC classification number: H03K19/018521 ,  H03K19/0948

Abstract: A current mode logic (CML)-complementary metal oxide semiconductor (CMOS) converter prevents change of a duty ratio to stably operate during an operation for converting a CML level signal into a CMOS level signal. The CML-CMOS converter includes a reference level shifting unit configured to receive a CML signal swinging about a first reference level to shift a swing reference level to a second reference level; and an amplifying unit configured to amplify an output signal of the reference level shifting unit to output the amplified signal as a CMOS signal.

Abstract translation: 电流模式逻辑（CML） - 互补金属氧化物半导体（CMOS）转换器在用于将CML电平信号转换为CMOS电平信号的操作期间防止占空比的变化以稳定地操作。 CML-CMOS转换器包括参考电平移位单元，被配置为接收围绕第一参考电平摆动的CML信号，以将摆幅参考电平移位到第二参考电平; 以及放大单元，被配置为放大参考电平移位单元的输出信号以输出放大的信号作为CMOS信号。

公开(公告)号：US07738621B2

公开(公告)日：2010-06-15

申请号：US12005933

申请日：2007-12-28

Applicant: Dae-Kun Yoon ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

Inventor： Dae-Kun Yoon ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC: G06M3/00 ,  H03K21/40

CPC classification number: G06M3/12

Abstract: A counter with overflow prevention capability includes a counting unit configured to count an output code in response to an input signal and an overflow preventing unit configured to control the counting unit to stop counting the output code when a current value of the output code is a maximum value but a previous value thereof is not the maximum value.

Abstract translation: 具有防溢能力的计数器包括：计数单元，被配置为响应于输入信号对输出代码进行计数;以及溢出防止单元，被配置为当输出代码的当前值为最大值时，控制计数单元停止计数输出代码 值，但其前一值不是最大值。

公开(公告)号：US20100142244A1

公开(公告)日：2010-06-10

申请号：US12483328

申请日：2009-06-12

Applicant: Kyung Hoon KIM ,  Sang Sic YOON

Inventor： Kyung Hoon KIM ,  Sang Sic YOON

IPC: G11C5/02 ,  G11C7/10 ,  G11C5/06

CPC classification number: G11C8/06 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045

Abstract: A memory module is configured to include a first rank installed with a first memory chip and a second rank installed with a second memory chip. When the first and second memory chips are in a first data output mode, the first memory chip is configured to externally output lower order data of a plurality of data via lower data output pins. Also, when the first and second memory chips are in the first data output mode, the second memory chip is configured to externally output data that has the same order as the lower order data output by the first memory chip via upper data output pins.

Abstract translation: 存储器模块被配置为包括安装有第一存储器芯片的第一等级和安装有第二存储器芯片的第二等级。 当第一和第二存储器芯片处于第一数据输出模式时，第一存储器芯片被配置为经由下部数据输出引脚从外部输出多个数据的低阶数据。 此外，当第一和第二存储器芯片处于第一数据输出模式时，第二存储器芯片被配置为从外部输出与第一存储器芯片经由上部数据输出引脚输出的与低级数据相同的顺序的数据。

公开(公告)号：US07724013B2

公开(公告)日：2010-05-25

申请号：US12076890

申请日：2008-03-25

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: G01R31/02

CPC classification number: G01R31/31708 ,  G01R31/3187 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12015 ,  G11C29/40 ,  G11C29/50 ,  G11C29/50012

Abstract: An on-chip self test circuit implemented on the same chip as a test semiconductor device includes: a test load block for receiving a test target signal; and a self test block for receiving a test target signal passing through the test load block and a test target signal inputted to an output driver together, and determining whether a change of the test target signal is within an allowable range.

Abstract translation: 在与测试半导体器件相同的芯片上实现的片上自检电路包括：用于接收测试目标信号的测试负载块; 以及自测试块，用于接收通过所述测试加载块的测试目标信号和输入到输出驱动器的测试目标信号，并且确定所述测试目标信号的改变是否在允许范围内。

公开(公告)号：US07710794B2

公开(公告)日：2010-05-04

申请号：US12215738

申请日：2008-06-30

Applicant: Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

Inventor： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076

Abstract: A semiconductor memory device can a desired internal clock in consideration of a delay time of an actual clock/data path. The semiconductor memory device includes a multiclock signal generating unit configured to receive a reference clock signal and generate a plurality of clock signals having a constant phase difference from each other, a delay modeling unit configured to generate a plurality of delay clock signals by reflecting a delay time of an actual clock/data path to the plurality of clock signals, a selection signal generating unit configured to generate selection signals by comparing phases between the reference clock signal and the plurality of delay clock signals, and a phase multiplexing unit configured to output any one of the plurality of clock signals as a final clock signal in response to the selection signals.

Abstract translation: 考虑到实际时钟/数据路径的延迟时间，半导体存储器件可以具有期望的内部时钟。 半导体存储器件包括多锁信号产生单元，被配置为接收参考时钟信号并产生彼此具有恒定相位差的多个时钟信号;延迟建模单元，被配置为通过反映延迟来产生多个延迟时钟信号 选择信号生成单元，被配置为通过比较参考时钟信号和多个延迟时钟信号之间的相位来产生选择信号;以及相位多路复用单元，被配置为输出任意的时钟/数据路径， 所述多个时钟信号中的一个作为响应于所述选择信号的最终时钟信号。

公开(公告)号：US07696831B2

公开(公告)日：2010-04-13

申请号：US12079443

申请日：2008-03-26

Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC: H03L7/085 ,  H03L7/089

CPC classification number: H03L7/0893 ,  H03L7/0896 ,  H03L7/0898

Abstract: Phase locked loop and method for controlling the same includes a phase/frequency detector configured to detect a phase difference between an input clock and a feedback clock to generate an up signal or a down signal depending on the detected phase difference, a charge pump configured to variably control a bandwidth according to a bandwidth control signal input thereinto, the charge pump operating in response to the up signal or the down signal and a voltage controlled oscillator configured to change a frequency according to an output of the charge pump.

Abstract translation: 锁相环及其控制方法包括相位/频率检测器，被配置为检测输入时钟和反馈时钟之间的相位差，以根据检测到的相位差产生上升信号或下降信号，电荷泵被配置为 根据其中输入的带宽控制信号可变地控制带宽，所述电荷泵响应于上升信号或下降信号而工作;以及压控振荡器，被配置为根据电荷泵的输出来改变频率。

公开(公告)号：US20090293205A1

公开(公告)日：2009-12-03

申请号：US12470818

申请日：2009-05-22

Applicant: Sun Cheol Bae ,  Kyung Hoon Kim ,  Han Su Jung ,  Jae Hyeok Choi ,  Ja In Koo

Inventor： Sun Cheol Bae ,  Kyung Hoon Kim ,  Han Su Jung ,  Jae Hyeok Choi ,  Ja In Koo

IPC: D06F33/00 ,  D06F39/00

CPC classification number: D06F33/02 ,  D06F2202/10 ,  D06F2204/065

Abstract: The present invention relates to a washing machine and a method of controlling the washing machine. According to a washing machine and a method of controlling the washing machine in accordance with the present invention, a drum operates at a first speed so that part of the laundry tumbles within the drum and another part of the laundry adheres to the drum. The laundry amount within the drum is sensed during the first speed operation. Operation commands for driving the drum after the first speed operation are changed based on the sensed laundry amount. Accordingly, at the time of the dehydration cycle, stability of the washing machine and laundry balancing can be ensured.

Abstract translation: 洗衣机及洗衣机的控制方法技术领域本发明涉及洗衣机及洗衣机的控制方法。 根据根据本发明的洗衣机和洗衣机的控制方法，鼓以第一速度操作，使得衣物的一部分在滚筒内滚动，另一部分衣物粘附在滚筒上。 在第一速度操作期间感测到滚筒内的衣物量。 在第一速度操作之后用于驱动滚筒的操作命令基于感测的衣物量而改变。 因此，在脱水循环时，可以确保洗衣机的稳定性和衣物平衡。

公开(公告)号：US20090284293A1

公开(公告)日：2009-11-19

申请号：US12343753

申请日：2008-12-24

Applicant: Kyung-Hoon Kim ,  Bo-Kyeom Kim

Inventor： Kyung-Hoon Kim ,  Bo-Kyeom Kim

IPC: H03K3/017

CPC classification number: H03K5/1565 ,  H03K2005/00065

Abstract: A duty correction circuit includes a duty ratio sensor for controlling a duty ratio sensing speed by a sensing speed control signal and outputting a correction signal by sensing a duty ratio of a clock, and a duty ratio corrector for controlling the duty ratio of the clock in response to the correction signal.

Abstract translation: 占空比校正电路包括占空比传感器，用于通过感测速度控制信号控制占空比感测速度，并通过感测时钟的占空比来输出校正信号;以及占空比校正器，用于控制时钟的占空比 响应于校正信号。

公开(公告)号：US20090245325A1

公开(公告)日：2009-10-01

申请号：US12463838

申请日：2009-05-11

Applicant: Kyung-Hoon KIM ,  Patrick B. Moran

Inventor： Kyung-Hoon KIM ,  Patrick B. Moran

IPC: G01K1/00

CPC classification number: G01K13/00 ,  G11C5/143 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/20 ,  G11C11/406 ,  G11C11/40626 ,  G11C2029/5002 ,  G11C2211/4061

Abstract: A semiconductor memory device includes a thermosensor that senses present temperatures of the device and confirms whether the temperature values are valid. The thermosensor includes a temperature sensing unit, a storage unit and an initializing unit. The temperature sensing unit senses temperatures in response to a driving signal. The storage unit stores output signals of the temperature sensing unit and outputs temperature values. The initializing unit initializes the storage unit after a predetermined time from an activation of the driving signal. A driving method includes driving the thermosensor in response to the driving signal, requesting a re-driving after a predetermined time from the activation of the driving signal, and re-driving the thermosensor in response to the driving signal input again.

Abstract translation: 半导体存储器件包括感测器件的当前温度并确认温度值是否有效的热敏传感器。 热敏传感器包括温度检测单元，存储单元和初始化单元。 温度感测单元响应于驱动信号感测温度。 存储单元存储温度感测单元的输出信号并输出​​温度值。 初始化单元在从驱动信号的激活开始的预定时间之后初始化存储单元。 驱动方法包括响应于驱动信号驱动热敏传感器，在从驱动信号的激活开始的预定时间之后请求重新驱动，并且响应于再次输入驱动信号重新驱动热敏传感器。

公开(公告)号：US20090167441A1

公开(公告)日：2009-07-02

申请号：US12217049

申请日：2008-06-30

Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC: H03L7/00 ,  H03L7/24

CPC classification number: H03L7/0812 ,  H03L7/18 ,  H03L7/24

Abstract: An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.

Abstract translation: 注入锁定时钟发生器可以改变注入锁定振荡器的自由运行频率，以扩大注入到其自身的振荡信号的工作频率范围，从而相对于工作频率范围的所有频率执行注入锁定。 时钟发生器包括：主振荡器，其被配置为产生与控制电压对应的频率的振荡信号;以及注入锁定振荡器，其被配置为通过划分所述振荡信号产生与所述振荡信号同步的除法信号，其中所述注入的自由运行频率 锁定振荡器根据振荡信号的频率设定。