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公开(公告)号：US20140321190A1
公开(公告)日：2014-10-30
申请号：US14282444
申请日：2014-05-20
Applicant: Daniel R. Shepard
Inventor： Daniel R. Shepard
CPC classification number: G11C8/10 , G11C13/0002 , G11C13/0004 , G11C13/0023 , G11C17/12 , G11C17/16 , G11C17/18 , G11C2213/71 , H01L27/1021 , H01L27/1027 , H01L27/105 , H01L27/112 , H01L27/11206 , H01L27/11517 , H01L27/2445 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L29/7827 , H01L29/87 , H01L45/04 , H01L45/06 , H01L45/124 , H01L45/144
Abstract: A memory device includes a substrate, and, disposed thereover, an array of vertical memory switches. In some embodiments, each switch has at least three terminals and a cross-sectional area less than 6 F2.
Abstract translation: 存储器件包括衬底，并且在其上设置有垂直存储器开关阵列。 在一些实施例中，每个开关具有至少三个端子和小于6F2的横截面面积。
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公开(公告)号：US20140131830A1
公开(公告)日：2014-05-15
申请号：US14078769
申请日：2013-11-13
Applicant: Daniel R. Shepard
Inventor： Daniel R. Shepard
IPC: H01L21/308 , H01L21/311 , H01L27/02
CPC classification number: H01L27/2463 , H01L21/0337 , H01L21/311 , H01L21/31144 , H01L27/1021 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
Abstract: In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.
Abstract translation: 在各种实施例中，用于形成存储器阵列的方法包括形成多个硬掩模材料的行和列，使用硬掩模材料行和硬掩模列的组合掩蔽特性来蚀刻绝缘材料的一个或多个层中的孔 材料，并在孔中形成记忆单元。 孔的角可以是圆形的。
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公开(公告)号：US08451024B2
公开(公告)日：2013-05-28
申请号：US13267985
申请日：2011-10-07
Applicant: Daniel R. Shepard
Inventor： Daniel R. Shepard
IPC: H03K19/0175 , H03K19/094
CPC classification number: H03K19/094 , H03K19/0013
Abstract: The present invention relates to electronic driver circuits, and more particularly, to low power electronic driver circuits having low manufacturing costs. The present invention is a circuit design that utilizes two transistor types that can be manufactured together thereby reducing the number of processing steps and masks and resulting in lower cost.
Abstract translation: 电子驱动电路技术领域本发明涉及电子驱动电路，更具体地说，涉及制造成本低的低功率电子驱动电路。 本发明是利用可以一起制造的两种晶体管类型的电路设计，从而减少处理步骤和掩模的数量并导致更低的成本。
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公开(公告)号：US08325557B2
公开(公告)日：2012-12-04
申请号：US12639599
申请日：2009-12-16
Applicant: Daniel R. Shepard
Inventor： Daniel R. Shepard
IPC: G11C8/00
CPC classification number: G11C7/02 , G11C29/83 , Y10T29/49002
Abstract: A memory device having a plurality of storage locations disposed along a plurality of generally parallel lines includes, connected to the lines, a decoder circuit for selecting one line, and, connected to each line, a line-disabling circuit for selectively preventing the line from being energized during line selection.
Abstract translation: 具有沿着多个大致平行的线路设置的多个存储位置的存储器件包括连接到线路的用于选择一条线路的解码器电路，并且连接到每条线路，用于选择性地防止线路 在选线期间通电。
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75.发明申请PRENYLTRANSFERASE INHIBITORS FOR OCULAR HYPERTENSION CONTROL AND THE TREATMENT OF GLAUCOMA 审中-公开用于高血压控制和GLAUCOMA治疗的PRENYLTRANSFERASE抑制剂公开(公告)号：US20120108632A1
公开(公告)日：2012-05-03
申请号：US13344258
申请日：2012-01-05
Applicant: Allan R. Shepard , Debra L. Fleenor
Inventor： Allan R. Shepard , Debra L. Fleenor
IPC: A61K31/4709 , A61K31/216 , C07D233/64 , A61P27/02 , C07C229/66 , A61K31/205 , A61K31/417
CPC classification number: A61K31/166 , A61K31/195 , A61K31/24 , A61K31/417 , A61K31/4172 , A61K31/4178 , A61K31/4709 , A61K31/557
Abstract: The invention concerns in one embodiment a method of treating glaucoma or elevated intraocular pressure comprising administering a pharmaceutically effective amount of a composition comprising at least one prenyltransferase inhibitor. In another embodiment, the invention concerns a composition for the treatment of elevated intraocular pressure and glaucoma comprising a pharmaceutically effective amount of a prenyltransferase inhibitor.
Abstract translation: 本发明在一个实施方案中涉及治疗青光眼或升高的眼内压的方法，其包括施用药学有效量的包含至少一种异戊烯基转移酶抑制剂的组合物。 在另一个实施方案中，本发明涉及用于治疗眼内压升高和青光眼的组合物，其包含药学有效量的异戊烯基转移酶抑制剂。
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Patent Agency Ranking
公开(公告)号：US20120086473A1
公开(公告)日：2012-04-12
申请号：US13267985
申请日：2011-10-07
Applicant: DANIEL R. SHEPARD
Inventor： DANIEL R. SHEPARD
IPC: H03K19/094
CPC classification number: H03K19/094 , H03K19/0013
Abstract: The present invention relates to electronic driver circuits, and more particularly, to low power electronic driver circuits having low manufacturing costs. The present invention is a circuit design that utilizes two transistor types that can be manufactured together thereby reducing the number of processing steps and masks and resulting in lower cost.
Abstract translation: 电子驱动电路技术领域本发明涉及电子驱动电路，更具体地说，涉及制造成本低的低功率电子驱动电路。 本发明是利用可以一起制造的两种晶体管类型的电路设计，从而减少处理步骤和掩模的数量并导致更低的成本。
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公开(公告)号：US08144622B2
公开(公告)日：2012-03-27
申请号：US12250410
申请日：2008-10-13
Applicant: John R. Shepard , Joe Nelson
Inventor： John R. Shepard , Joe Nelson
IPC: H04L12/28
CPC classification number: H04W40/24 , G05B2219/21079 , G05B2219/25061 , G05B2219/25101 , G05B2219/31121 , G05B2219/31123 , G05B2219/31151 , G05B2219/33192 , H04W8/20 , H04W76/14 , Y02P90/10 , Y02P90/18 , Y02P90/86
Abstract: A wireless communication system for use in a process environment uses mesh and possibly a combination of mesh and point-to-point communications to produce a wireless communication network that can be easily set up, configured, changed and monitored, thereby making a wireless communication network that is less expensive, and more robust and reliable. The wireless communication system allows virtual communication paths to be established and used within the process control system in a manner that is independent of the manner in which the wireless signals are sent between different wireless transmitting and receiving devices within the process plant, to thereby operate in a manner that is independent of the specific messages or virtual communication paths within the process plant. Still further, communication analysis tools are provided to enable a user or operator to view the operation of the wireless communication network to thereby analyze the ongoing operation of the wireless communications within the wireless communication network.
Abstract translation: 在过程环境中使用的无线通信系统使用网格以及可能的网格和点对点通信的组合来产生可以容易地建立，配置，改变和监视的无线通信网络，从而形成无线通信网络 这是更便宜，更强大和可靠。 无线通信系统允许在过程控制系统内建立和使用虚拟通信路径，其方式是独立于无线信号在过程工厂内的不同无线发送和接收设备之间发送的方式，从而在 一种独立于过程工厂内的特定消息或虚拟通信路径的方式。 还提供了通信分析工具，以使用户或操作者能够查看无线通信网络的操作，从而分析无线通信网络内的无线通信的正在进行的操作。
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公开(公告)号：US08035416B1
公开(公告)日：2011-10-11
申请号：US12827545
申请日：2010-06-30
Applicant: Daniel R. Shepard
Inventor： Daniel R. Shepard
IPC: H03K19/094
CPC classification number: H03K19/094 , H03K19/0013
Abstract: The present invention relates to electronic driver circuits, and more particularly, to low power electronic driver circuits having low manufacturing costs. The present invention is a circuit design that utilizes two transistor types that can be manufactured together thereby reducing the number of processing steps and masks and resulting in lower cost.
Abstract translation: 电子驱动电路技术领域本发明涉及电子驱动电路，更具体地说，涉及制造成本低的低功率电子驱动电路。 本发明是利用可以一起制造的两种晶体管类型的电路设计，从而减少处理步骤和掩模的数量并导致更低的成本。
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79.发明授权公开(公告)号：US08000129B2
公开(公告)日：2011-08-16
申请号：US12339696
申请日：2008-12-19
Applicant: Daniel R. Shepard
Inventor： Daniel R. Shepard
IPC: G11C13/00
CPC classification number: G11C13/0023 , B82Y10/00 , G11C13/0004
Abstract: Embodiments of the present invention include systems and methods for three-terminal field-emitter triode devices, and memory arrays utilizing the same. In other embodiments, the field-emitter devices include a volume-change material, capable of changing a measurable electrical property of the devices, and/or three-dimensional memory arrays of the same.
Abstract translation: 本发明的实施例包括用于三端子场致发射三极管器件的系统和方法，以及利用其的存储器阵列。 在其他实施例中，场致发射器件包括能够改变器件的可测量电性能的体积变化材料和/或其中的三维存储器阵列。
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公开(公告)号：US20110019468A1
公开(公告)日：2011-01-27
申请号：US12873501
申请日：2010-09-01
Applicant: Daniel R. Shepard
Inventor： Daniel R. Shepard
Abstract: A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that is non-selected, and a low resistance when connected to the selected row and column.
Abstract translation: 高速，低功率存储器件包括非线性导体阵列，其中存储，地址解码和输出检测全部由二极管或其它非线性导体完成。 在各种实施例中，行和列电阻器可以在连接到未选择的行或列之间的高电阻之间切换，并且当连接到所选择的行和列时可以是低电阻。
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