公开(公告)号：US12280466B2

公开(公告)日：2025-04-22

申请号：US17825449

申请日：2022-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyug Lee ,  Chae Lyoung Kim ,  Hoyoung Kim ,  Seungjun Lee

IPC: B24B37/04 ,  B24B37/07

Abstract: Disclosed are substrate polishing apparatuses, substrate polishing systems, and/or substrate polishing methods. The substrate polishing apparatus may include an electric field applying module, and a platen that rotates a polishing pad. The electric field applying module may include an inner electrode having a circular shape when viewed in plan. The platen may be on the inner electrode. A central axis of the inner electrode may be spaced apart from a central axis of the platen. The inner electrode may include a first electrode and a second electrode that may surround the first electrode and may have an annular shape.

公开(公告)号：US12280325B2

公开(公告)日：2025-04-22

申请号：US17750884

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd. ,  POSTECH Research and Business Development Foundation

Inventor： Hyoungwoo Choi ,  Hyomin Lee ,  Min Ryu ,  Jinkyu Kang ,  Joonseon Jeong ,  Dongwook Kim ,  Daehoon Park ,  Hyun Chul Lee

IPC: B01D47/06 ,  B01D39/20 ,  B01D46/00 ,  B01D46/02 ,  B05D5/08 ,  B82B3/00 ,  B82Y30/00 ,  B82Y40/00

Abstract: A porous composite structure including a substrate including a plurality of nanostructures; a particle layer disposed on a surface of the substrate; and a liquid, a method of preparing the porous composite structure, an article including the porous composite structure, and an air purifier including the porous composite structure.

公开(公告)号：US20250126903A1

公开(公告)日：2025-04-17

申请号：US18990000

申请日：2024-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongsoon KANG ,  Mintae RYU ,  Minsu LEE ,  Wonsok LEE

IPC: H10F39/18 ,  H10F39/00 ,  H10F39/15

Abstract: An image sensor includes a first substrate. A photoelectric conversion region is in the first substrate. A first interlayer insulating layer is on the first substrate. A transistor includes a bonding insulating layer on the first interlayer insulating layer, a semiconductor layer on the bonding insulating layer, and a first gate on the semiconductor layer. A bias pad is spaced apart from the semiconductor layer by the bonding insulating layer. The bias pad overlaps the first gate in a planar view. A second interlayer insulating layer covers the transistor.

公开(公告)号：US20250126875A1

公开(公告)日：2025-04-17

申请号：US18913129

申请日：2024-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae LEE ,  Seunggeol NAM ,  Donghoon KIM ,  Sijung YOO ,  Dukhyun CHOE

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

Abstract: Provided is a semiconductor device including a channel layer including a semiconductor material, a ferroelectric layer arranged on the channel layer and including a ferroelectric material, a gate electrode arranged on the ferroelectric layer, a first insertion layer arranged between the ferroelectric layer and the gate electrode and including a first paraelectric material, and a second insertion layer arranged between the channel layer and the ferroelectric layer and including a second paraelectric material having a dielectric constant higher than a dielectric constant of the first paraelectric material.

公开(公告)号：US20250126864A1

公开(公告)日：2025-04-17

申请号：US19001779

申请日：2024-12-26

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Minsu SEOL ,  Hyeonsuk SHIN ,  Hyeonjin SHIN ,  Hyuntae HWANG ,  Changseok LEE ,  Seongin YOON

IPC: H10D62/82 ,  H01L21/02 ,  H10D48/36 ,  H10D62/80 ,  H10D62/85

Abstract: Provided are a black phosphorus-two dimensional material complex and a method of manufacturing the black phosphorus-two dimensional material complex. The black phosphorus-two dimensional material complex includes: first and second two-dimensional material layers, which each have a two-dimensional crystal structure and are coupled to each other by van der Waals force; and a black phosphorus sheet which between the first and second two-dimensional material layers and having a two-dimensional crystal structure in which a plurality of phosphorus atoms are covalently bonded.

公开(公告)号：US20250126835A1

公开(公告)日：2025-04-17

申请号：US18625457

申请日：2024-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjin LEE ,  Min Tae RYU ,  Younggeun SONG ,  Sanghoon AHN ,  Min Hee CHO ,  Daewon HA

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device may include peripheral circuit structures on a substrate, an interlayer insulating layer on the peripheral circuit structure, a bit line extending in a first direction in the interlayer insulating layer, a semiconductor pattern on the bit line, and including first and second vertical portions facing each other in the first direction and a horizontal portion connecting the first and second vertical portions to each other, first and second word lines on the horizontal portion and adjacent to the first and second vertical portions, respectively, and a gate insulating pattern interposed between the first vertical portion and the first word line, and between the second vertical portion and the second word line. An upper surface of the interlayer insulating layer and an upper surface of the bit line are coplanar with each other.

公开(公告)号：US20250126790A1

公开(公告)日：2025-04-17

申请号：US18756161

申请日：2024-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minyong Lee ,  Jiyoung Kim ,  Sehoon Lee ,  Junhyoung Kim ,  Sukkang Sung

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10B43/40

Abstract: An example non-volatile memory device includes a substrate including a first cell region, a second cell region, and a connection region between the first cell region and the second cell region, a mold structure including a plurality of gate electrodes being stacked in a stepped pattern in a pad region, a trench along a profile of the mold structure on the pad region, the trench including a bottom surface having a stair shape and a first sidewall on a boundary between the pad region and a wall region, a liner film on the first sidewall of the trench, a recess in the trench and exposing a pad portion of a gate electrode, a cell contact provided at the recess and connected with the pad portion, and a cover insulating layer provided at the trench. The liner film has a different etch selectivity with respect to the cover insulating layer.

公开(公告)号：US20250126733A1

公开(公告)日：2025-04-17

申请号：US19002694

申请日：2024-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongseok LEE ,  Byounguk YOON

IPC: H05K5/02

Abstract: An electronic device according to one embodiment includes: a housing including a through-hole; a printed circuit board; and a tray which moves to the outside of the through-hole according to movement in the first direction, or of which at least one portion is arranged on the printed circuit board according to movement in the second direction in order to be inserted into the through-hole, where the tray includes: a first accommodation hole for insertion of an external member penetrating the outer surface of the tray; and an elastic member which includes an insertion hole, and which can be deformed by the external member, and the tray is inserted into the insertion hole so as to be movable to the outside of the through-hole by movement in the first direction of the external member in contact with the elastic member.

公开(公告)号：US20250126626A1

公开(公告)日：2025-04-17

申请号：US18904335

申请日：2024-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juhyuk IM

IPC: H04W72/25 ,  H03M13/39 ,  H04W4/40

Abstract: An operation method of a wireless communication device for performing sidelink-based vehicle-to-everything (V2X) communication includes decoding first sidelink control information (SCI) to obtain a first decoding result, the first SCI being contained in a received physical sidelink control channel (PSCCH), decoding second SCI including obtaining a plurality of log likelihood ratio (LLR) values by demodulating the second SCI, storing the plurality of LLR values in a plurality of deinterleaving buffers such that the plurality of LLR values are deinterleaved, and decoding the plurality of LLR values stored in the plurality of deinterleaving buffers to obtain a second decoding result, the second SCI being contained in a physical sidelink shared channel (PSSCH), and the PSSCH being received based on the first decoding result, and decoding the PSSCH based on the second decoding result.

公开(公告)号：US20250126512A1

公开(公告)日：2025-04-17

申请号：US18909089

申请日：2024-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chadi KHIRALLAH ,  Mahmoud WATFA ,  Erik GUTTMAN

IPC: H04W28/02 ,  H04W52/36

Abstract: The disclosure relates to a 5th generation (5G) or 6th generation (6G) communication system for supporting a higher data transmission rate. A method performed by a network entity in a wireless communications network is provided. The method includes obtaining energy information associated with the wireless communications network and determining, based on the energy information, at least one of a quality of service (QoS) profile associated with a QoS flow of the wireless communications network and a QoS profile associated with a user equipment (UE).