公开(公告)号：US07800427B2

公开(公告)日：2010-09-21

申请号：US11986345

申请日：2007-11-21

Applicant: Youngcheol Chae ,  Gunhee Han ,  Seog-Heon Ham

Inventor： Youngcheol Chae ,  Gunhee Han ,  Seog-Heon Ham

IPC: G06G7/184 ,  H03M3/02

CPC classification number: H03H19/004 ,  H03M3/356 ,  H03M3/43 ,  H03M3/456

Abstract: A switched capacitor circuit includes an amplifier, a charging unit, an offset unit, and an integrating unit. The charging unit is coupled between an input node and a first node, and is for accumulating charge corresponding to an input signal during a sampling mode. The offset unit is coupled between the first node and an input of the amplifier, and is for maintaining the first node to be a virtual ground during an integrating mode. The integrating unit is coupled between the first node and an output of the amplifier, and is for receiving charge from the charging unit during the integrating mode.

Abstract translation: 开关电容电路包括放大器，充电单元，偏移单元和积分单元。 充电单元耦合在输入节点和第一节点之间，并且用于在采样模式期间累加对应于输入信号的电荷。 偏移单元耦合在第一节点和放大器的输入之间，并且用于在积分模式期间将第一节点维持为虚拟地面。 积分单元耦合在第一节点和放大器的输出端之间，用于在积分模式期间从充电单元接收电荷。

公开(公告)号：US07629838B2

公开(公告)日：2009-12-08

申请号：US11975018

申请日：2007-10-17

Applicant: Seung-Hyun Lim ,  Jeong-Hwan Lee ,  Gun-Hee Han ,  Seog-Heon Ham

Inventor： Seung-Hyun Lim ,  Jeong-Hwan Lee ,  Gun-Hee Han ,  Seog-Heon Ham

IPC: H03F1/02

CPC classification number: H03F3/005 ,  H03F3/45475 ,  H03F2203/45514 ,  H03F2203/45551

Abstract: A ratio-independent switched capacitor amplifier includes a first sampling circuit configured to sample a first input voltage as a first sampling voltage and to double a level of the first sampling voltage during an interval in which the first input voltage is cut off; a second sampling circuit configured to sample a second input voltage as a second sampling voltage and to double a level of the second sampling voltage during an interval in which the second input voltage is cut off; and a differential amplifier circuit configured to output a difference between the first sampling voltage and the second sampling voltage.

Abstract translation: 比率无关的开关电容放大器包括：第一采样电路，被配置为将第一输入电压作为第一采样电压进行采样，并在第一输入电压被切断的间隔期间使第一采样电压的电平加倍; 第二采样电路，被配置为将第二输入电压作为第二采样电压进行采样，并且在所述第二输入电压被切断的间隔期间将所述第二采样电压的电平加倍; 以及差分放大电路，被配置为输出第一采样电压和第二采样电压之间的差。

公开(公告)号：US20090295956A1

公开(公告)日：2009-12-03

申请号：US12453593

申请日：2009-05-15

Applicant: Youngcheol Chae ,  In Hee Lee ,  Jimin Cheon ,  Gunhee Han ,  Seog Heon Ham

Inventor： Youngcheol Chae ,  In Hee Lee ,  Jimin Cheon ,  Gunhee Han ,  Seog Heon Ham

IPC: H04N3/14 ,  G06F17/17 ,  H03M1/12

CPC classification number: H04N5/37455 ,  H03H17/0664 ,  H03M3/424 ,  H03M3/462

Abstract: An image sensor includes an analog-to-digital converter (ADC) and a decimation filter. The decimation filter includes a first digital data generator and a second digital data generator. The first digital data generator is configured to integrate sigma-delta modulated M-bit pixel data and output N-bit pixel data based on an integration result. The second digital data generator is configured to integrate the N-bit pixel data, generate P-bit pixel data based on an integration result, and output the P-bit pixel data as decimated data.

Abstract translation: 图像传感器包括模数转换器（ADC）和抽取滤波器。 抽取滤波器包括第一数字数据发生器和第二数字数据发生器。 第一数字数据发生器被配置为基于积分结果来集成Σ-Δ调制的M位像素数据和输出N位像素数据。 第二数字数据发生器被配置为集成N位像素数据，基于积分结果产生P位像素数据，并将P位像素数据输出为抽取数据。

公开(公告)号：US20080111906A1

公开(公告)日：2008-05-15

申请号：US11985012

申请日：2007-11-13

Applicant: Dong-Soo Kim ,  Gun-Hee Han ,  Seog-Heon Ham

Inventor： Dong-Soo Kim ,  Gun-Hee Han ,  Seog-Heon Ham

IPC: H04N5/335 ,  H01L27/146

CPC classification number: H01L27/14603 ,  H01L27/14645 ,  H01L2924/0002 ,  H04N5/35554 ,  H04N5/37452 ,  H01L2924/00

Abstract: Provided is a pixel circuit in a CMOS image sensor, a structure thereof, and a method of operating the same. The pixel includes: a photodiode; a floating diffusion node connected to the photodiode through a first switch; a source follower responsive to a voltage of the floating diffusion node. The voltage of the floating diffusion node is applied to the source follower through capacitance coupling.

Abstract translation: 提供了一种CMOS图像传感器中的像素电路及其结构及其操作方法。 像素包括：光电二极管; 通过第一开关连接到所述光电二极管的浮动扩散节点; 响应于浮动扩散节点的电压的源极跟随器。 通过电容耦合将浮动扩散节点的电压施加到源极跟随器。

公开(公告)号：US5977595A

公开(公告)日：1999-11-02

申请号：US878483

申请日：1997-06-18

Applicant: Seog-heon Ham

Inventor： Seog-heon Ham

IPC: H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/085 ,  H01L23/62

CPC classification number: H01L27/027 ,  H01L27/0288

Abstract: The present invention relates to an apparatus and method for protecting a semiconductor device, and more particularly to an n-type metal-oxide semiconductor (NMOS) transistor with a ladder structure, used for protecting a semiconductor device from electrostatic discharge. In the present invention, a plurality of drain branches are connected by resistors, and a contact point of the well and the source/well pattern is formed only alongside the drain branch of the ladder structure which is nearest an input/output terminal of the semiconductor device. Accordingly, the current is better dispersed to all of the drain branches, thereby preventing the voltage breakdown of the transistor due to heat caused by the localization of current in the drain branch farthest from the input/output terminal.

Abstract translation: 本发明涉及用于保护半导体器件的装置和方法，更具体地涉及用于保护半导体器件免于静电放电的具有梯形结构的n型金属氧化物半导体（NMOS）晶体管。 在本发明中，多个漏极分支通过电阻器连接，并且阱和源极/阱图案的接触点仅沿梯形结构的漏极分支形成，其最靠近半导体的输入/输出端子 设备。 因此，电流更好地分散到所有的漏极分支，从而防止由于在离输入/输出端子最远的漏极支路中的电流的定位引起的由于热引起的晶体管的电压击穿。

公开(公告)号：US5898193A

公开(公告)日：1999-04-27

申请号：US963105

申请日：1997-11-03

Applicant: Seog-Heon Ham

Inventor： Seog-Heon Ham

IPC: H01L27/06 ,  H01L27/02 ,  H01L29/74 ,  H01L23/62 ,  H01L29/00

CPC classification number: H01L27/0255

Abstract: Disclosed is an electrostatic discharge (ESD) protecting circuit, capable of consuming a high voltage or overcurrent applied to a semiconductor circuit device and thereby protecting the circuit device from the instant ESD impact. The ESD protecting circuit according to this invention has only two wells and a highly doped region which brings an N-well into an electrical connection with the P-well. Accordingly, the present invention provides effects of reducing the area of the ESD protecting circuit and removing an instant ESD impact.

Abstract translation: 公开了一种静电放电（ESD）保护电路，其能够消耗施加到半导体电路器件的高电压或过电流，从而保护电路器件免受即时ESD冲击。 根据本发明的ESD保护电路仅具有两个阱和高掺杂区域，其使N阱与P阱电连接。 因此，本发明提供减小ESD保护电路的面积并消除即时ESD冲击的效果。

公开(公告)号：US5874763A

公开(公告)日：1999-02-23

申请号：US753939

申请日：1996-12-02

Applicant: Seog-Heon Ham

Inventor： Seog-Heon Ham

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L27/10 ,  H01L29/78

CPC classification number: H01L27/0266

Abstract: Integrated circuits having improved electrostatic discharge capability include MOS transistors having wide channel widths formed by patterning a plurality of MOS transistor cells side-by-side in a well region as a highly integrated ladder network. The drain regions of the MOS transistor cells are coupled to an input pad to be protected and the source regions of the MOS transistor cells are coupled to a reference signal line (e.g., GND, VSS). The gate electrodes of the MOS transistor cells are also coupled together and indirectly through the well region to the reference signal line. The gates electrodes are coupled to the well region so that at the onset of reverse P-N junction breakdown between one or more of the drain regions (e.g., N-type) and the well region (e.g., P-type), the potentials of the gate electrodes of the MOS transistor cells are increased. This increase in gate electrode potential causes the breakdown voltages of the other nonconducting drain regions to be lowered to initiate breakdown so that the electrostatic discharge current can be more uniformly shared by all of the MOS transistor cells.

Abstract translation: 具有改善的静电放电能力的集成电路包括MOS晶体管，其具有宽的沟道宽度，其通过在阱区中并排地构成多个MOS晶体管单元而形成，作为高度集成的梯形网络。 MOS晶体管单元的漏极区域被耦合到要被保护的输入焊盘，并且MOS晶体管单元的源极区域被耦合到参考信号线（例如，GND，VSS）。 MOS晶体管单元的栅电极也耦合在一起并间接地通过阱区耦合到参考信号线。 栅电极耦合到阱区，使得在一个或多个漏区（例如，N型）和阱区（例如P型）之间的反向PN结击穿开始时， MOS晶体管单元的栅电极增加。 栅电极电位的增加导致其它非导通漏极区的击穿电压降低以引起击穿，使得静电放电电流可以被所有MOS晶体管单元更均匀地共享。

公开(公告)号：US5731614A

公开(公告)日：1998-03-24

申请号：US752960

申请日：1996-12-02

Applicant: Seog-Heon Ham

Inventor： Seog-Heon Ham

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/60 ,  H01L27/02 ,  H01L27/092 ,  H01L27/10 ,  H01L23/62

CPC classification number: H01L27/0266

Abstract: A plurality of transistors are aligned to form a ladder structure between two well contacts in a semiconductor substrate, the ladder structure including a plurality of elongate gate contacts extending parallel to one another, a plurality of elongate source contacts extending parallel to one another, and a plurality of elongate drain contacts extending parallel to one another, wherein the source contacts and the drain contacts are alternately arranged between the gate contacts. In the ladder structure, a first distance is made greater than a second distance to prevent current localization at respective junctions between a first drain contact and adjacent gate contacts located on opposite sides of the first drain contact, the first drain contact being a one of the plurality of drain contacts which is spaced furthest away from both the two well contacts. The first distance is a distance between the first drain contact and each of the adjacent gate contacts located on opposite sides of the first drain contact, and the second distance is a distance between each of the remaining drain contacts and each of the gate contacts adjacent to the remaining drain contacts.

Abstract translation: 多个晶体管被对准以在半导体衬底中的两个阱触点之间形成梯形结构，梯形结构包括彼此平行延伸的多个细长栅极触点，彼此平行延伸的多个细长源极触点，以及 多个细长的漏极触点彼此平行延伸，其中源触点和漏极触点交替地布置在栅极触点之间。 在梯形结构中，使第一距离大于第二距离，以防止在位于第一漏极接触的相对侧上的第一漏极接触和相邻栅极接触之间的各个接点处的电流定位，第一漏极接触是 多个漏极触点，其间隔离两个阱触点最远。 第一距离是第一漏极接触和位于第一漏极接触的相对侧上的每个相邻栅极接触之间的距离，第二距离是每个剩余的漏极接触和每个邻近的栅极接触之间的距离 剩余的漏极触点。