公开(公告)号：US20120066903A1

公开(公告)日：2012-03-22

申请号：US13306811

申请日：2011-11-29

申请人： RUI-WU LIU ,  YUNG-WEI LAI ,  SHING-TZA LIOU

发明人： RUI-WU LIU ,  YUNG-WEI LAI ,  SHING-TZA LIOU

IPC分类号： H05K3/42

CPC分类号： H05K3/4084 ,  H05K3/326 ,  H05K2201/0397 ,  H05K2201/10598 ,  H05K2203/0165 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167

摘要： A method for manufacturing a FPCB substrate includes the following steps. First, a FPCB material including an insulation layer and an electrically conductive layer formed on the insulation layer is provided. The electrically conductive layer has a first surface and an opposite second surface. The insulation layer has a third surface and an opposite fourth surface. The third surface comes into contact with the second surface. Secondly, a through hole extends from the first surface to the fourth surface is formed. The through hole includes a metal hole in the electrically conductive layer and an insulation hole in the insulation layer. Thirdly, the insulation hole is enlarged to expose a portion of the electrically conductive layer around the metal hole. Finally, the exposed portion is bent to form a hook which passes through the enlarged insulation hole and protrudes out from the fourth surface of the insulation layer.

摘要翻译： FPCB基板的制造方法包括以下步骤。 首先，提供一种包含绝缘层和形成在绝缘层上的导电层的FPCB材料。 导电层具有第一表面和相对的第二表面。 绝缘层具有第三表面和相对的第四表面。 第三表面与第二表面接触。 其次，形成从第一表面延伸到第四表面的通孔。 通孔包括导电层中的金属孔和绝缘层中的绝缘孔。 第三，扩大绝缘孔，使金属孔周围的一部分导电层露出。 最后，暴露部分被弯曲以形成通过扩大的绝缘孔并从绝缘层的第四表面突出的钩。

公开(公告)号：US08099408B2

公开(公告)日：2012-01-17

申请号：US12163895

申请日：2008-06-27

申请人： Lei Zhang ,  Wei-Ying Ma ,  Wei Lai ,  Jiangming Yang ,  Rui Cai

发明人： Lei Zhang ,  Wei-Ying Ma ,  Wei Lai ,  Jiangming Yang ,  Rui Cai

IPC分类号： G06F7/06 ,  G06F17/30

CPC分类号： G06F17/30864

摘要： A method and system for identifying informative links of a web site for use in crawling the web site is provided. A forum crawler analyzes sample web pages of a web forum to identify informative links and then crawls the web forum by following links determined to be informative and not following other links. The forum crawler system determines whether links are informative based on whether they are part of the overall structure of the web site or are used to select sequential information that has been split onto multiple web pages.

摘要翻译： 提供了一种用于识别用于爬行网站的网站的信息链接的方法和系统。 论坛搜寻器分析网页论坛的示例网页，以识别信息链接，然后通过确定为信息而不是遵循其他链接的链接抓取网页论坛。 论坛搜寻器系统基于它们是网站的整体结构的一部分还是用于选择分割到多个网页上的顺序信息来确定链接是否具有信息性。

公开(公告)号：US08072260B1

公开(公告)日：2011-12-06

申请号：US12951486

申请日：2010-11-22

申请人： Gregory Starr ,  Kang Wei Lai ,  Richard Y. Chang

发明人： Gregory Starr ,  Kang Wei Lai ,  Richard Y. Chang

IPC分类号： H01L25/00

CPC分类号： H03K19/017581 ,  G06F1/10

摘要： In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.

摘要翻译： 在具有高速串行接口通道的可编程逻辑器件中，用于向这些高速串行接口的动态相位对准电路提供一个或多个高速时钟的时钟分配网络包括至少一个可分段的总线（例如使用可调 缓冲区）。 这允许总线在高速串行接口以不同的速度运行时被分成不同的部分，可以连接到不同的时钟源。 在一个实施例中，分段元件（例如，上述缓冲器）位于所选择的通道（例如，每第四通道）之间，限制不同段的大小。 在另一个实施例中，分段元件位于每个通道之间，允许完全用户在选择段的大小时的自由度。 因此，代替为每个时钟源提供总线，通过分割单个总线，可以使多个时钟可用于不同的通道。

公开(公告)号：US08052881B2

公开(公告)日：2011-11-08

申请号：US12164422

申请日：2008-06-30

申请人： Yun-Li Zhu ,  Yung-Wei Lai ,  Shing-Tza Liou

发明人： Yun-Li Zhu ,  Yung-Wei Lai ,  Shing-Tza Liou

IPC分类号： H05K13/00

CPC分类号： H05K3/4638 ,  H05K1/0269 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/09063 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0156 ,  H05K2203/166 ,  Y10T29/49128 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T156/10

摘要： A method for manufacturing a multilayer printed circuit board includes the following steps. A number of laminate units are provided. Each of the laminate units includes an electrically conductive layer with a circuit pattern defined therein, and a release layer releasably attached to the electrically conductive layer. A number of insulation layers are provided. Each of the insulation layers definies a metalized through hole therein. The electrically conductive layers and the insulation layers are stacked alternately one on another such that adjacent electrically conductive layers are insulated by one insulation layer and the metalized through holes electrically connects the circuit patterns of the adjacent electrically conductive layers. In the stacking step, the release layer is removed from the laminate unit after the electrically conductive layer is stacked onto the respective insulation layer, thereby obtaining a pre-laminated multilayer printed circuit board. The stacked electrically conductive layers and the insulation layers are laminated together to achieve a multilayer printed circuit board.

摘要翻译： 一种制造多层印刷电路板的方法包括以下步骤。 提供了许多层压单元。 每个层压单元包括其中限定有电路图案的导电层和可剥离地附接到导电层的剥离层。 提供了许多绝缘层。 每个绝缘层在其中确定了金属化的通孔。 导电层和绝缘层交替地堆叠在一起，使得相邻的导电层被一个绝缘层绝缘，并且金属化的通孔电连接相邻的导电层的电路图案。 在堆叠步骤中，在将导电层堆叠在各绝缘层上之后，从层压单元中去除剥离层，从而获得预层压多层印刷电路板。 层叠的导电层和绝缘层被层叠在一起以实现多层印刷电路板。

公开(公告)号：US20110082174A1

公开(公告)日：2011-04-07

申请号：US12939276

申请日：2010-11-04

申请人： John M. BRACKETT ,  David T. JONAITIS ,  Wei LAI ,  Jih Hua LIU ,  Stephan D. PARENT ,  Jinyu SHEN

发明人： John M. BRACKETT ,  David T. JONAITIS ,  Wei LAI ,  Jih Hua LIU ,  Stephan D. PARENT ,  Jinyu SHEN

IPC分类号： A61K31/4439 ,  C07D401/14 ,  A61P1/04

CPC分类号： C07D401/14

摘要： The invention relates to crystalline forms of racemic ilaprazole, 2[[(4-methoxy-3-methyl-2-pyridinyl)-methyl]sulfinyl]-5-(1H-pyrrol-1-yl) 1H-Benzimidazole. The invention also relates to a pharmaceutical composition for inhibiting gastric acid secretion comprising a crystalline Form of ilaprazole according to the invention in an amount effective to inhibit gastric acid secretion and a pharmaceutically acceptable carrier. The invention also provides methods of treatment for various acid-related gastrointestinal (GI) disorders.

公开(公告)号：US20110051298A1

公开(公告)日：2011-03-03

申请号：US12548586

申请日：2009-08-27

申请人： Da-Wei Lai

发明人： Da-Wei Lai

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： In some embodiments, an electrostatic discharge (ESD) protection circuit includes a substrate resistance control circuit coupled to a body of a first NMOS transistor. The substrate resistance control circuit increases a resistance of the body of the first NMOS transistor during an ESD event. The first NMOS transistor has a drain coupled to an input/output (I/O) pad and a gate coupled to a first voltage source. The first voltage source is set at ground potential.

摘要翻译： 在一些实施例中，静电放电（ESD）保护电路包括耦合到第一NMOS晶体管的主体的衬底电阻控制电路。 衬底电阻控制电路在ESD事件期间增加了第一NMOS晶体管的主体的电阻。 第一NMOS晶体管具有耦合到输入/输出（I / O）焊盘和耦合到第一电压源的栅极的漏极。 第一个电压源设置在地电位。

公开(公告)号：US07883668B2

公开(公告)日：2011-02-08

申请号：US11949563

申请日：2007-12-03

申请人： Shen-Kan Hsiung ,  Jung-Chuan Chou ,  Tai-Ping Sun ,  Nien-Hsuan Chou ,  Chih-Wei Lai

发明人： Shen-Kan Hsiung ,  Jung-Chuan Chou ,  Tai-Ping Sun ,  Nien-Hsuan Chou ,  Chih-Wei Lai

IPC分类号： G01J1/48

CPC分类号： G01N21/783

摘要： An optical gas concentration sensor and method for measuring blood gas based on the light adsorption sensing technique are disclosed. The optical gas concentration sensor comprises a light source, a photo detector, and a gas filtering membrane for separating the indicator and a liquid. A gas in the liquid diffuses to the indicator through the gas filtering membrane so as to change the color of the indicator due to the chemical reaction occurred between the indicator and the gas. Then, the photo detector receives the light passing though the reacted indicator from the light source. The gas concentration is determined based on pH-sensitive absorbance spectrum of the indicator.

摘要翻译： 公开了一种基于光吸收传感技术测量血液气体的光学气体浓度传感器和方法。 光学气体浓度传感器包括用于分离指示剂和液体的光源，光电检测器和气体过滤膜。 液体中的气体通过气体过滤膜扩散到指示器，以便由于指示剂和气体之间发生化学反应而改变指示器的颜色。 然后，光检测器从光源接收通过反应指示器的光。 基于指示剂的pH敏感吸收光谱确定气体浓度。

公开(公告)号：US20110007452A1

公开(公告)日：2011-01-13

申请号：US12713398

申请日：2010-02-26

申请人： Ching-Feng Lin ,  Yui-Hsin Fran ,  Chi-Hao Chiu ,  Ming-Tsung Chen ,  Cheng-Wei Lai ,  Chun-Chia Huang

发明人： Ching-Feng Lin ,  Yui-Hsin Fran ,  Chi-Hao Chiu ,  Ming-Tsung Chen ,  Cheng-Wei Lai ,  Chun-Chia Huang

IPC分类号： H01G9/15

CPC分类号： H01G9/012 ,  H01G2/06 ,  H01G9/15

摘要： A lamellar stacked solid electrolytic capacitor includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit is composed of a negative foil, an isolation paper with conductive polymer substance, a positive foil, an isolation paper with conductive polymer substance and a negative foil that are stacked onto each other in sequence, the positive foils of the capacitor units are electrically connected to each other, the negative foils of the capacitor units are electrically connected to each other, and the positive foils and the negative foils are insulated from each other. The substrate unit has a positive guiding substrate electrically connected to the positive foils of the capacitor units and a negative guiding substrate electrically connected to the negative foils of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit.

摘要翻译： 片状堆叠固体电解电容器包括多个电容器单元，基板单元和封装单元。 每个电容器单元由负箔，具有导电聚合物物质的隔离纸，正箔，具有导电聚合物物质的隔离纸和负箔依次堆叠组成，电容器单元的正箔是 彼此电连接，电容器单元的负箔彼此电连接，并且正箔和负箔彼此绝缘。 基板单元具有电连接到电容器单元的正箔的正引导基板和电连接到电容器单元的负箔的负引导基板。 封装单元覆盖电容器单元和衬底单元的一部分。

公开(公告)号：US20100328827A1

公开(公告)日：2010-12-30

申请号：US12824571

申请日：2010-06-28

申请人： Da-Wei LAI ,  Wade MA

发明人： Da-Wei LAI ,  Wade MA

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad. The ESD protection circuit includes a clamp field effect transistor (FET) coupled between a first supply voltage and a second supply voltage. An inverter includes an input end and an output end. The output end of the inverter is coupled with a gate of the clamp FET. A RC time constant circuit is disposed between the first supply voltage and the second supply voltage. A current mirror includes a first transistor. The current minor is coupled between the input end of the inverter and the second supply voltage. A circuit is coupled with the input end of the inverter. The circuit is capable of outputting a voltage state on the input end of the inverter that is capable of substantially turning off the clamp FET while the I/O pad is subjected to a latch-up test using a negative current.

摘要翻译： 与输入/输出（I / O）接口耦合的静电放电（ESD）保护电路。 ESD保护电路包括耦合在第一电源电压和第二电源电压之间的钳位场效应晶体管（FET）。 逆变器包括输入端和输出端。 反相器的输出端与钳位FET的栅极耦合。 RC时间常数电路设置在第一电源电压和第二电源电压之间。 电流镜包括第一晶体管。 电流调节器耦合在逆变器的输入端和第二电源电压之间。 电路与逆变器的输入端耦合。 该电路能够在逆变器的输入端输出电压状态，该电压状态能够在使用负电流对I / O焊盘进行闩锁测试的同时基本上关断钳位FET。

公开(公告)号：US07767471B2

公开(公告)日：2010-08-03

申请号：US11830519

申请日：2007-07-30

申请人： Jean Wang ,  Francis Ko ,  Henry Lo ,  Chi-Chun Hsieh ,  Amy Wang ,  Chih-Wei Lai ,  Chun-Hsien Lin

发明人： Jean Wang ,  Francis Ko ,  Henry Lo ,  Chi-Chun Hsieh ,  Amy Wang ,  Chih-Wei Lai ,  Chun-Hsien Lin

IPC分类号： H01L21/00 ,  G01R31/26

CPC分类号： H01L22/12

摘要： A method for improving within-wafer uniformity is provided. The method includes forming an electrical component by a first process step and a second process step, wherein the electrical component has a target electrical parameter. The method includes providing a first plurality of production tools for performing the first process step; providing a second plurality of production tools for performing the second process step; providing a wafer; performing the first process step on the wafer using one of the first plurality of production tools; and selecting a first route including a first production tool from the second plurality of production tools. A within-wafer uniformity of the target electrical parameter on the wafer manufactured by the first route is greater than a second route including a second production tool in the second plurality of production tools.

摘要翻译： 提供了一种提高晶片内均匀性的方法。 该方法包括通过第一处理步骤和第二处理步骤形成电子部件，其中电气部件具有目标电参数。 该方法包括提供用于执行第一处理步骤的第一多个生产工具; 提供用于执行所述第二处理步骤的第二多个生产工具; 提供晶片; 使用所述第一多个生产工具之一在所述晶片上执行所述第一工艺步骤; 以及从所述第二多个生产工具中选择包括第一生产工具的第一路线。 由第一路径制造的晶片上的目标电参数的晶片内均匀性大于在第二多个生产工具中包括第二生产工具的第二路线。