公开(公告)号：US08098500B2

公开(公告)日：2012-01-17

申请号：US12234245

申请日：2008-09-19

Applicant: Tae Won Heo ,  Gun Woo Moon ,  Woo Jin Lee ,  Ki Bum Park ,  Don Sik Kim ,  Chong Eun Kim ,  Jong Pil Kim ,  Sang Cheol Bong ,  Hak Ryong Kim ,  Dong Joong Kim

Inventor： Tae Won Heo ,  Gun Woo Moon ,  Woo Jin Lee ,  Ki Bum Park ,  Don Sik Kim ,  Chong Eun Kim ,  Jong Pil Kim ,  Sang Cheol Bong ,  Hak Ryong Kim ,  Dong Joong Kim

IPC: H02M3/335 ,  H02M3/18

CPC classification number: H02M3/33592 ,  H02M3/337 ,  H02M2007/4818 ,  H02M2007/53878 ,  Y02B70/1441 ,  Y02B70/1475

Abstract: A phase shift full bridge converter with a reduced current stress includes: a switching unit that switches an input voltage; a transformer that includes a first capacitor serially connected to, and having a primary side and a secondary side; an auxiliary circuit unit that includes a first switch, a second switch, and a second capacitor, which are connected in parallel to the secondary side of the transformer; and a rectification unit that is connected to the auxiliary circuit unit, with an output inductor being removed.

Abstract translation: 具有减小的电流应力的相移全桥转换器包括：切换输入电压的开关单元; 变压器，其包括串联连接到第一电容器并且具有初级侧和次级侧的第一电容器; 辅助电路单元，其包括与变压器的次级侧并联连接的第一开关，第二开关和第二电容器; 以及整流单元，其连接到辅助电路单元，其中输出电感器被去除。

公开(公告)号：US08003174B2

公开(公告)日：2011-08-23

申请号：US11955766

申请日：2007-12-13

Applicant: Atsuki Fukazawa ,  Woo Jin Lee ,  Nobuo Matsuki

Inventor： Atsuki Fukazawa ,  Woo Jin Lee ,  Nobuo Matsuki

IPC: H05H1/24

CPC classification number: C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/3122 ,  H01L21/3125 ,  H01L21/31612

Abstract: A method of forming a dielectric film, includes: introducing a siloxane gas essentially constituted by Si, O, C, and H and a silazane gas essentially constituted by Si, N, H, and optionally C into a reaction chamber where a substrate is placed; depositing a siloxane-based film including Si—N bonds on the substrate by plasma reaction; and annealing the siloxane-based film on the substrate in an annealing chamber to remove Si—N bonds from the film.

Abstract translation: 形成电介质膜的方法包括：将基本上由Si，O，C和H构成的硅氧烷气体和基本上由Si，N，H和任选的C组成的硅氮烷气体引入放置基板的反应室中 ; 通过等离子体反应在衬底上沉积包含Si-N键的硅氧烷基膜; 并在退火室中退火基板上的硅氧烷基膜，以从膜中除去Si-N键。

公开(公告)号：US20110014795A1

公开(公告)日：2011-01-20

申请号：US12832739

申请日：2010-07-08

Applicant: Woo Jin Lee ,  Kuo-Wei Hong ,  Akira Shimizu

Inventor： Woo Jin Lee ,  Kuo-Wei Hong ,  Akira Shimizu

IPC: H01L21/318

CPC classification number: H01L21/3141 ,  C23C16/345 ,  C23C16/45538 ,  C23C16/5096 ,  C23C16/52 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3185

Abstract: A method of forming stress-tuned dielectric films having Si—N bonds on a semiconductor substrate by modified plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen-and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space using a high frequency RF power source and a low frequency RF power source; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a stress-tuned dielectric film having Si—N bonds on the substrate.

Abstract translation: 通过改进的等离子体增强原子层沉积（PEALD）在半导体衬底上形成具有Si-N键的应力调谐电介质膜的方法包括：将含氮和氢的反应气体和添加气体引入到反应空间内 放置半导体衬底; 使用高频RF电源和低频RF电源将RF功率应用于反应空间; 并将脉冲中的含氢硅前体引入反应空间，其中等离子体被激发，从而在衬底上形成具有Si-N键的应力调谐电介质膜。

公开(公告)号：US07707469B2

公开(公告)日：2010-04-27

申请号：US11892846

申请日：2007-08-28

Applicant: Woo-Jin Lee ,  Seok-Won Hwang

Inventor： Woo-Jin Lee ,  Seok-Won Hwang

IPC: G11C29/00

CPC classification number: G11C29/02 ,  G11C29/022 ,  G11C29/025

Abstract: Example embodiments relate to a memory test system having a semiconductor memory device, a coupling circuit and a tester. The semiconductor memory device may include a plurality of first output nodes and a plurality of second output nodes. The first output nodes may be connected to respective first on-die termination circuits that may not be tested, and the second output nodes may be connected to second on-die termination circuits that may be tested. The semiconductor memory device may be configured to generate test signals of the second on-die termination circuits and to provide the test signals to the second output nodes. The coupling circuit may be configured to connect the first output nodes and the second output nodes to communication channels, respectively. The tester may be configured to test a logic state of the test signals of the communication channels.

Abstract translation: 示例实施例涉及具有半导体存储器件，耦合电路和测试器的存储器测试系统。 半导体存储器件可以包括多个第一输出节点和多个第二输出节点。 第一输出节点可以连接到可能不被测试的相应的第一片上终端电路，并且第二输出节点可以连接到可以被测试的第二片上终端电路。 半导体存储器件可以被配置为产生第二片上终端电路的测试信号，并将测试信号提供给第二输出节点。 耦合电路可以被配置为分别将第一输出节点和第二输出节点连接到通信信道。 测试器可以被配置为测试通信信道的测试信号的逻辑状态。

公开(公告)号：US20100081470A1

公开(公告)日：2010-04-01

申请号：US12422924

申请日：2009-04-13

Applicant: Woo-Jin Lee ,  Kyoung-Taek Lim ,  Byung-Duck Park ,  Sang-Chul Jeon

Inventor： Woo-Jin Lee ,  Kyoung-Taek Lim ,  Byung-Duck Park ,  Sang-Chul Jeon

IPC: H04M1/00

CPC classification number: H04M1/22 ,  H04M1/0237 ,  H04M2250/22 ,  H04M2250/52

Abstract: A mobile terminal includes a housing comprising a light emitting portion disposed on at least a portion of the housing, a light emitting unit disposed inside the housing, a light transmission member configured to transmit light emitted from the light emitting unit, and a guiding structure formed on the light transmission member and configured to direct and emit the light toward the light emitting portion.

Abstract translation: 移动终端包括壳体，其包括设置在壳体的至少一部分上的发光部分，设置在壳体内部的发光单元，被配置为透射从发光单元发射的光的光传输部件和形成的引导结构 在所述光传输部件上并且被配置为朝向所述发光部分引导和发射所述光。

公开(公告)号：US20090156017A1

公开(公告)日：2009-06-18

申请号：US11955766

申请日：2007-12-13

Applicant: Atsuki FUKAZAWA ,  Woo Jin LEE ,  Nobuo MATSUKI

Inventor： Atsuki FUKAZAWA ,  Woo Jin LEE ,  Nobuo MATSUKI

IPC: H01L21/31

CPC classification number: C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/3122 ,  H01L21/3125 ,  H01L21/31612

Abstract: A method of forming a dielectric film, includes: introducing a siloxane gas essentially constituted by Si, O, C, and H and a silazane gas essentially constituted by Si, N, H, and optionally C into a reaction chamber where a substrate is placed; depositing a siloxane-based film including Si—N bonds on the substrate by plasma reaction; and annealing the siloxane-based film on the substrate in an annealing chamber to remove Si—N bonds from the film.

Abstract translation: 形成电介质膜的方法包括：将基本上由Si，O，C和H构成的硅氧烷气体和基本上由Si，N，H和任选的C组成的硅氮烷气体引入放置基板的反应室中 ; 通过等离子体反应在衬底上沉积包含Si-N键的硅氧烷基膜; 并在退火室中退火基板上的硅氧烷基膜，以从膜中除去Si-N键。

公开(公告)号：US07478954B2

公开(公告)日：2009-01-20

申请号：US11737255

申请日：2007-04-19

Applicant: In Kui Cho ,  Woo Jin Lee ,  Sang Pil Han ,  Seung Ho Ahn ,  Gyung Ock Kim ,  Hee Kyung Sung

Inventor： In Kui Cho ,  Woo Jin Lee ,  Sang Pil Han ,  Seung Ho Ahn ,  Gyung Ock Kim ,  Hee Kyung Sung

IPC: G02B6/43 ,  G02B6/30 ,  G02B6/36

CPC classification number: G02B6/43 ,  G02B6/2552 ,  G02B6/4202 ,  G02B6/4239 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Provided are a method and structure for optical connection between an optical transmitter and an optical receiver. The method includes the steps of: forming on a substrate a light source device, an optical detection device, an optical transmission unit electrically connected with the light source device, and an optical detection unit electrically connected with the optical detection device; preparing a flexible optical transmission-connection medium to optically connect the light source device with the optical detection device; cutting the prepared optical transmission-connection medium and surface-finishing it; and connecting one end of the surface-finished optical transmission-connection medium with the light source device and the other end with the optical detection device. Fabrication of an optical package having a 3-dimensional structure is facilitated and fabrication time is reduced, thus improving productivity. In addition, since the optical transmission-connection medium is directly connected with the light source device and the optical detection device, a polishing operation or additional connection block is not required, thus facilitating mass production.

Abstract translation: 提供了一种用于光发射机和光接收机之间的光连接的方法和结构。 该方法包括以下步骤：在基板上形成光源装置，光检测装置，与光源装置电连接的光传输单元以及与该光检测装置电连接的光检测单元; 准备柔性光传输连接介质以将光源装置与光学检测装置光学连接; 切割准备的光传输连接介质并进行表面处理; 并且将表面光整传输连接介质的一端与光源装置连接，另一端与光学检测装置连接。 促进了具有3维结构的光学封装的制造，并减少了制造时间，从而提高了生产率。 此外，由于光传输连接介质与光源装置和光学检测装置直接连接，因此不需要抛光操作或附加连接块，因此便于批量生产。

公开(公告)号：US20080112669A1

公开(公告)日：2008-05-15

申请号：US11974635

申请日：2007-10-15

Applicant: Choon Gi Choi ,  Young Tak Han ,  Jin Tae Kim ,  Woo Jin Lee

Inventor： Choon Gi Choi ,  Young Tak Han ,  Jin Tae Kim ,  Woo Jin Lee

IPC: G02B6/34 ,  G03F1/08

CPC classification number: G02B6/1225 ,  B82Y20/00 ,  G02B6/1221

Abstract: Provided are a two-dimensional planar photonic crystal superprism device and a method of manufacturing the same, in which a manufacturing process is simplified using a nanoimprint lithography technique, and thus price-reduction and mass production are facilitated. The two-dimensional planar photonic crystal superprism device includes: a single-mode input waveguide comprising a straight waveguide having a taper structure and a bending waveguide; a superprism formed on an output end side of the single-mode input waveguide and comprising a slab and a photonic crystal superprism; and a single-mode output waveguide comprising a straight waveguide having a taper structure and a bending waveguide, and formed adjacent to the photonic crystal superprism. Using the two-dimensional planar photonic crystal superprism device, it is possible to facilitate manufacturing of nano-photonic integrated circuits, photonic crystal integrated circuits and nano-photonic systems. In addition, a wavelength-selectable photonic crystal superprism device using high dispersion of photonic crystal, which is several hundred times the dispersion of conventional glass prism, can be manufactured using thermal/hot and ultraviolet nanoimprint lithography techniques corresponding to nano-manufacturing technology.

Abstract translation: 提供了一种二维平面光子晶体超控装置及其制造方法，其中使用纳米压印光刻技术简化了制造工艺，因此有利于价格降低和批量生产。 二维平面光子晶体超导装置包括：单模输入波导，包括具有锥形结构的直波导管和弯曲波导; 形成在单模输入波导的输出端侧并且包括平板和光子晶体超控的超实例; 以及单模输出波导，其包括具有锥形结构的直波导管和弯曲波导，并且与光子晶体超立体相邻地形成。 使用二维平面光子晶体超微元器件，可以促进纳米光子集成电路，光子晶体集成电路和纳米光子系统的制造。 此外，使用对应于纳米制造技术的热/热和紫外线纳米压印光刻技术可以制造使用高分散度的光子晶体的波长可选择的光子晶体超大容量器件，其是常规玻璃棱镜的百分之几。

公开(公告)号：US20070290902A1

公开(公告)日：2007-12-20

申请号：US11802886

申请日：2007-05-25

Applicant: Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Woo-Jin Lee

Inventor： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Woo-Jin Lee

IPC: H03M9/00

CPC classification number: H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract translation: 提供半导体器件，包括所述半导体器件的系统及其方法。 半导体器件的示例可以接收被调度用于发送的数据，对接收到的数据内的比特数进行加扰，按照给定的伪随机序列排列的加扰顺序。 所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。 然后可以发送平衡和加扰的接收数据。 示例半导体器件可以以任何顺序执行加扰和平衡操作。 类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。 可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

公开(公告)号：US20070188201A1

公开(公告)日：2007-08-16

申请号：US11566651

申请日：2006-12-04

Applicant: Hyun-Jin KIM ,  Seong-Jin JANG ,  Kwang-Il PARK ,  Woo-Jin LEE

Inventor： Hyun-Jin KIM ,  Seong-Jin JANG ,  Kwang-Il PARK ,  Woo-Jin LEE

IPC: H03B1/00

CPC classification number: H03K19/0013 ,  H03K19/018521

Abstract: A circuit including a voltage boost circuit coupled to a first node and a second node, and configured to apply a boosted first node voltage to the second node; and an inverter circuit coupled to the first node, the second node, and a third node, and configured to generate a signal on the third node in response to the signals on the first node and the second node.

Abstract translation: 一种电路，包括耦合到第一节点和第二节点的升压电路，并且被配置为将升压的第一节点电压施加到所述第二节点; 以及反相器电路，其耦合到所述第一节点，所述第二节点和第三节点，并且被配置为响应于所述第一节点和所述第二节点上的信号而在所述第三节点上生成信号。