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公开(公告)号:US09159381B2
公开(公告)日:2015-10-13
申请号:US13464242
申请日:2012-05-04
申请人: Xia Li , Jung Pill Kim , Taehyun Kim
发明人: Xia Li , Jung Pill Kim , Taehyun Kim
CPC分类号: G11C7/062 , G11C11/16 , G11C11/1673 , G11C11/5642
摘要: A circuit includes a first reference pair that includes a first path and a second path. The first path includes a first magnetic tunnel junction (MTJ) element, and the second path includes a second MTJ element. The circuit further includes a second reference pair that includes a third path and a fourth path. The third path includes a third MTJ element, and the fourth path includes a fourth MTJ element. The first reference pair and the second reference pair are tied together in parallel. A reference resistance of the circuit is based on a resistance of each of the first, second, third, and fourth MTJ elements. The reference resistance of the circuit is adjustable by adjusting a resistance of one of the MTJ elements.
摘要翻译: 电路包括包括第一路径和第二路径的第一参考对。 第一路径包括第一磁隧道结(MTJ)元件,第二路径包括第二MTJ元件。 电路还包括第二参考对,其包括第三路径和第四路径。 第三路径包括第三MTJ元件,第四路径包括第四MTJ元件。 第一个参考对和第二个参考对并联在一起。 电路的参考电阻基于第一,第二,第三和第四MTJ元件中的每一个的电阻。 通过调整MTJ元件之一的电阻可以调节电路的参考电阻。
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公开(公告)号:US09064589B2
公开(公告)日:2015-06-23
申请号:US13356720
申请日:2012-01-24
申请人: Xia Li , Xiaochun Zhu , Seung H. Kang , Jung Pill Kim , Wah Nam Hsu , Taehyun Kim , Kangho Lee
发明人: Xia Li , Xiaochun Zhu , Seung H. Kang , Jung Pill Kim , Wah Nam Hsu , Taehyun Kim , Kangho Lee
CPC分类号: G11C11/161 , G11C8/16 , G11C11/16 , G11C11/1659 , H01L27/228 , H01L43/08
摘要: A two-transistor one-MTJ (2T1MTJ) three port structure includes two separate pin layer structures coupled to one free layer structure. The pin layer structures may include an anti-ferromagnetic layer (AFM) layer coupled to a pin layer. The free layer structure includes free layer coupled to a barrier layer and a cap layer. The free layer structure may include a thin barrier layer coupled to each of the pin layer stacks. The three port MTJ structure provides separate write and read paths which improve read sensing margin without increasing write voltage or current. The three port MTJ structure may be fabricated with a simple two step MTJ etch process.
摘要翻译: 双晶体管单MTJ(2T1MTJ)三端口结构包括耦合到一个自由层结构的两个独立的引脚层结构。 引脚层结构可以包括耦合到引脚层的反铁磁层(AFM)层。 自由层结构包括耦合到阻挡层和盖层的自由层。 自由层结构可以包括耦合到每个引脚层堆叠的薄势垒层。 三端口MTJ结构提供单独的写入和读取路径,从而提高读取感测余量,而不增加写入电压或电流。 三端口MTJ结构可以用简单的两步MTJ蚀刻工艺制造。
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公开(公告)号:US08912012B2
公开(公告)日:2014-12-16
申请号:US12626269
申请日:2009-11-25
申请人: Xia Li , Seung H. Kang , Xiaochun Zhu
发明人: Xia Li , Seung H. Kang , Xiaochun Zhu
CPC分类号: H01L43/12 , G11C11/15 , G11C11/161 , H01L21/00 , H01L27/224 , H01L43/08 , H04W52/12 , H04W52/26 , H04W52/34 , H04W52/44 , H04W52/54 , H04W72/1231 , H04W72/1247 , H04W72/1252 , H04W88/08 , H04W88/12
摘要: A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction structure above a bottom electrode. The method also includes forming a diffusion barrier layer above and adjacent to the magnetic tunnel junction structure. The method further includes etching back the diffusion barrier layer, removing the diffusion barrier layer above the magnetic tunnel junction structure. The method also includes connecting a top of the magnetic tunnel junction structure to a conductive layer.
摘要翻译: 公开了一种磁性隧道结(MTJ)器件及其制造方法。 在特定实施例中,公开了一种方法,其包括在底部电极上形成磁性隧道结结构。 该方法还包括在磁隧道结结构上方并邻近形成扩散阻挡层。 该方法还包括蚀刻扩散阻挡层,去除在磁性隧道结结构上方的扩散阻挡层。 该方法还包括将磁性隧道结结构的顶部连接到导电层。
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公开(公告)号:US08866242B2
公开(公告)日:2014-10-21
申请号:US13293310
申请日:2011-11-10
申请人: Xia Li , Seung H. Kang , Matthew M. Nowak
发明人: Xia Li , Seung H. Kang , Matthew M. Nowak
IPC分类号: H01L29/82 , H01L27/22 , H01L21/02 , G11C11/00 , G11C11/14 , G11C11/15 , H01L43/12 , H01L43/08 , H01L21/00
CPC分类号: H01L43/12 , H01L27/222 , H01L43/08
摘要: A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack.
摘要翻译: 存储器件可以包括磁性隧道结(MTJ)堆叠,底部电极(BE)层和接触层。 MTJ堆叠可以包括自由层,阻挡层和钉扎层。 BE层可以耦合到MTJ堆叠,并且封装在平坦化层中。 BE层也可以具有与MTJ叠层相当的共同轴。 接触层可以嵌入在BE层中,并且在BE层和MTJ堆叠之间形成界面。
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公开(公告)号:US08681536B2
公开(公告)日:2014-03-25
申请号:US12777529
申请日:2010-05-11
申请人: Seung H. Kang , Xia Li , Wei-Chuan Chen , Kangho Lee , Xiaochun Zhu , Wah Nam Hsu
发明人: Seung H. Kang , Xia Li , Wei-Chuan Chen , Kangho Lee , Xiaochun Zhu , Wah Nam Hsu
IPC分类号: G11C11/22
摘要: A magnetic tunnel junction (MTJ) with direct contact is manufactured having lower resistances, improved yield, and simpler fabrication. The lower resistances improve both read and write processes in the MTJ. The MTJ layers are deposited on a bottom electrode aligned with the bottom metal. An etch stop layer may be deposited adjacent to the bottom metal to prevent overetch of an insulator surrounding the bottom metal. The bottom electrode is planarized before deposition of the MTJ layers to provide a substantially flat surface. Additionally, an underlayer may be deposited on the bottom electrode before the MTJ layers to promote desired characteristics of the MTJ.
摘要翻译: 具有直接接触的磁性隧道结(MTJ)被制造成具有较低的电阻,提高的产量和更简单的制造。 较低的电阻提高了MTJ中的读取和写入过程。 MTJ层沉积在与底部金属对准的底部电极上。 蚀刻停止层可以沉积在底部金属附近,以防止围绕底部金属的绝缘体的过蚀刻。 在沉积MTJ层之前将底部电极平坦化以提供基本平坦的表面。 另外,可以在MTJ层之前的底部电极上沉积底层以促进MTJ的期望特性。
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公开(公告)号:US08680592B2
公开(公告)日:2014-03-25
申请号:US12780174
申请日:2010-05-14
申请人: Xia Li
发明人: Xia Li
CPC分类号: H01L43/12 , B82Y25/00 , B82Y40/00 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/5607 , G11C2211/5615 , H01F10/3254 , H01F41/308 , H01L27/222 , H01L43/08
摘要: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a first sidewall, a second sidewall, a third sidewall, a fourth sidewall, and a bottom wall. The method includes depositing a first conductive material within the trench proximate to the first sidewall and depositing a second conductive material within the trench. The method further includes depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure that is adjacent to the fourth sidewall to create an opening such that the MTJ structure is substantially u-shaped.
摘要翻译: 公开了一种形成磁性隧道结装置的方法,其包括在衬底中形成沟槽,所述沟槽包括第一侧壁,第二侧壁,第三侧壁,第四侧壁和底壁。 该方法包括在第一侧壁附近的沟槽内沉积第一导电材料,并在沟槽内沉积第二导电材料。 该方法还包括在沟槽内沉积磁性隧道结(MTJ)结构。 MTJ结构包括具有固定磁性取向的磁场的固定磁性层,隧道结层和具有可配置磁性取向的磁场的自由磁性层。 该方法还包括选择性地去除与第四侧壁相邻的MTJ结构的一部分以形成开口,使得MTJ结构基本上为U形。
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公开(公告)号:US20140071739A1
公开(公告)日:2014-03-13
申请号:US13613100
申请日:2012-09-13
申请人: Jung Pill Kim , Taehyun Kim , Sungryul Kim , Xia Li
发明人: Jung Pill Kim , Taehyun Kim , Sungryul Kim , Xia Li
IPC分类号: G11C11/16
CPC分类号: G11C11/1675 , G11C7/12 , G11C11/16
摘要: A tunable reference cell scheme for magnetic random access memory (MRAM) circuitry selectively couples reference cells and data cells to shared write driver circuitry. Magnetic tunnel junctions (MTJs) in the reference cells can be programmed to a selected magnetic orientation using the shared write driver circuitry. The programmed reference cells can be merged with other programmed reference cells and/or with fixed reference cells to produce a tunable reference level for comparison with MTJ data cells during a read operation. Sharing write driver circuitry between data cells and reference cells allows programming of reference cells without consuming increased area on a chip or macro.
摘要翻译: 用于磁随机存取存储器(MRAM)电路的可调谐参考单元方案选择性地将参考单元和数据单元耦合到共享写入驱动器电路。 可以使用共享写入驱动器电路将参考单元中的磁隧道结(MTJ)编程为选定的磁方向。 编程的参考单元可以与其他编程的参考单元和/或与固定参考单元合并,以产生可读参考水平,以便在读操作期间与MTJ数据单元进行比较。 在数据单元和参考单元之间共享写入驱动器电路可以编程参考单元,而不会消耗芯片或宏上的增加的面积。
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公开(公告)号:US20140048894A1
公开(公告)日:2014-02-20
申请号:US13589426
申请日:2012-08-20
申请人: Xia Li , Kangho Lee , Jung Pill Kim , Taehyun Kim , Wah Nam Hsu , Seung H. Kang , Xiaochun Zhu , Wei-Chuan Chen , Sungryul Kim
发明人: Xia Li , Kangho Lee , Jung Pill Kim , Taehyun Kim , Wah Nam Hsu , Seung H. Kang , Xiaochun Zhu , Wei-Chuan Chen , Sungryul Kim
CPC分类号: H01L43/12 , G11C11/005 , G11C11/161 , G11C11/1675 , G11C11/1693 , G11C11/5607 , G11C17/02 , G11C17/165 , H01L27/222 , H01L27/228 , H01L43/02 , H01L43/08
摘要: Systems and methods for multiple-time programmable (MTP) devices. An MTP device includes a magnetic tunnel junction (MTJ) device programmable to a plurality of states based on voltage applied across the MTJ device. The plurality of states include a first resistance state corresponding to a first binary value stored in the MTJ device based on a first voltage, a second resistance state corresponding to a second binary value stored in the MTJ device based on a second voltage, a third resistance state corresponding to a breakdown of a barrier layer of the MTJ device based on a third voltage, and a fourth resistance state corresponding to an open fuse based on a fourth voltage.
摘要翻译: 多时间可编程(MTP)设备的系统和方法。 MTP设备包括基于跨越MTJ设备施加的电压而可编程为多个状态的磁隧道结(MTJ)设备。 多个状态包括基于第一电压而存储在MTJ装置中的第一二进制值的第一电阻状态,基于第二电压存储在MTJ装置中的与第二二进制值对应的第二电阻状态,第三电阻 状态对应于基于第三电压的MTJ装置的势垒层的击穿,以及对应于基于第四电压的开路保险丝的第四电阻状态。
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公开(公告)号:US20140027774A1
公开(公告)日:2014-01-30
申请号:US13472075
申请日:2012-05-15
申请人: Xia Li , Christopher Vineis , Martin U. Pralle
发明人: Xia Li , Christopher Vineis , Martin U. Pralle
IPC分类号: H01L31/105
CPC分类号: H01L31/1055 , H01L31/02363 , H01L31/0747 , Y02E10/50
摘要: Photovoltaic heterojunction devices, combination hetero- homo-junction devices, and associated methods are provided. In one aspect, for example, a photovoltaic device can include a doped semiconductor substrate having a first textured region and a second textured region opposite the first textured region, a first intrinsic semiconductor layer coupled to the first textured region opposite the semiconductor substrate and a second intrinsic semiconductor layer coupled to the second textured region opposite the semiconductor substrate. A first semiconductor layer can be coupled to the first intrinsic semiconductor layer opposite the first textured region, where the first semiconductor layer is doped to an opposite polarity of the doped semiconductor substrate. A second semiconductor layer can be coupled to the second intrinsic semiconductor layer opposite the second textured region, where the second semiconductor layer is doped to a same polarity as the semiconductor substrate but having a higher dopant concentration as the semiconductor substrate.
摘要翻译: 提供了光伏异质结器件,组合异质结器件和相关方法。 在一个方面,例如,光伏器件可以包括具有第一纹理区域和与第一纹理化区域相对的第二纹理化区域的掺杂半导体衬底,耦合到与半导体衬底相对的第一纹理化区域的第一本征半导体层, 本征半导体层耦合到与半导体衬底相对的第二纹理区域。 第一半导体层可以耦合到与第一纹理化区域相对的第一本征半导体层,其中第一半导体层被掺杂到掺杂半导体衬底的相反极性。 第二半导体层可以耦合到与第二纹理化区域相对的第二本征半导体层,其中第二半导体层被掺杂到与半导体衬底相同的极性,但是具有较高的掺杂剂浓度作为半导体衬底。
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公开(公告)号:US08582354B1
公开(公告)日:2013-11-12
申请号:US13464060
申请日:2012-05-04
申请人: Xia Li , Wah Nam Hsu , Jung Pill Kim , Taehyun Kim , Seung H. Kang
发明人: Xia Li , Wah Nam Hsu , Jung Pill Kim , Taehyun Kim , Seung H. Kang
CPC分类号: G11C29/50 , G11C7/065 , G11C11/16 , G11C11/1673 , G11C11/5607 , G11C13/004 , G11C29/02 , G11C29/027 , G11C29/4401 , G11C29/50008 , G11C29/56
摘要: Methods and apparatus for testing a resistive memory element are provided. In an example, an initial test resistor in a resistance network coupled to a first input of a sense amplifier is selected, where the resistive memory element is coupled to a second input of the sense amplifier and an output of the sense amplifier is measured. Another test resistor is selected based on the output of the sense amplifier and both the measuring the output step and the selecting another test resistor step are repeated until the output of the sense amplifier changes. A resistance of the resistive memory element is estimated based on the last test resistor selected, where the selected test resistors and the resistive memory element pass respective currents having substantially similar amplitudes and are coupled to respective access transistors having substantially similar properties.
摘要翻译: 提供了用于测试电阻式存储元件的方法和装置。 在一个示例中,选择耦合到读出放大器的第一输入的电阻网络中的初始测试电阻器,其中电阻性存储器元件耦合到读出放大器的第二输入端,并测量读出放大器的输出。 基于读出放大器的输出选择另一个测试电阻器,并重复测量输出步骤,并重复选择另一个测试电阻器步骤,直到读出放大器的输出发生变化。 基于所选择的最后一个测试电阻来估计电阻性存储器元件的电阻,其中所选择的测试电阻器和电阻性存储器元件通过具有基本相似幅度的相应电流,并且耦合到具有基本上相似性质的相应的存取晶体管。
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