公开(公告)号：US08364086B2

公开(公告)日：2013-01-29

申请号：US12741952

申请日：2008-06-30

Applicant: Taegyun Noh ,  Byung Jang Jeong ,  Hyun Kyu Chung ,  Dae Woon Lim ,  Min Joong Lim ,  Ho Yun Kim ,  Yong June Kim

Inventor： Taegyun Noh ,  Byung Jang Jeong ,  Hyun Kyu Chung ,  Dae Woon Lim ,  Min Joong Lim ,  Ho Yun Kim ,  Yong June Kim

IPC: H04B1/00 ,  H04B15/00

CPC classification number: H04L1/206

Abstract: Disclosed are an apparatus and method of determining an optimal cyclic delay value. The method of determining the optimal cyclic delay value includes determining a Signal-to-Interference and Noise Ratio (SINR) function depending on a diversity order; determining a channel estimation error variance function; and determining an SINR being required for a system according to the SINR function and the channel estimation error variance function.

Abstract translation: 公开了一种确定最佳循环延迟值的装置和方法。 确定最佳循环延迟值的方法包括根据分集顺序确定信号与干扰和噪声比（SINR）函数; 确定信道估计误差方差函数; 以及根据SINR功能和信道估计误差方差函数确定系统所需的SINR。

公开(公告)号：US08281217B2

公开(公告)日：2012-10-02

申请号：US12379746

申请日：2009-02-27

Applicant: Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong

Inventor： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong

IPC: G11C29/00

CPC classification number: H03M13/2903 ,  G06F11/1072 ,  H03M13/29 ,  H03M13/353

Abstract: Memory devices and/or encoding/decoding methods are provided. A memory device may include: a memory cell array; an internal decoder configured to apply, to a first codeword read from the memory cell array, a first decoding scheme selected based on a characteristic of a first channel in which the first codeword is read to perform error control codes (ECC) decoding of the first codeword, and apply, to a second codeword read from the memory cell array, a second decoding scheme selected based on a characteristic of a second channel in which the second codeword is read to perform the ECC decoding of the second codeword; and an external decoder configured to apply an external decoding scheme to the ECC-decoded first codeword and the ECC-decoded second codeword to perform the ECC decoding of the first codeword and the second codeword.

Abstract translation: 提供存储器件和/或编码/解码方法。 存储器件可以包括：存储器单元阵列; 内部解码器，被配置为向从存储器单元阵列读取的第一代码字应用基于第一通道的特性选择的第一解码方案，其中读取第一代码字以执行第一代码字的错误控制代码（ECC）解码 代码字，并且应用于从存储单元阵列读取的第二码字，基于第二通道的特性选择的第二解码方案，其中读取第二码字以执行第二码字的ECC解码; 以及外部解码器，被配置为将外部解码方案应用于ECC解码的第一码字和ECC解码的第二码字，以执行第一码字和第二码字的ECC解码。

公开(公告)号：US20120221775A1

公开(公告)日：2012-08-30

申请号：US13407333

申请日：2012-02-28

Applicant: Yong June KIM ,  Hong Rak SON ,  Jae Hong KIM ,  Sang Yong YOON ,  Ki Jun LEE ,  Jung Soo CHUNG ,  Seong Hyeog CHOI

Inventor： Yong June KIM ,  Hong Rak SON ,  Jae Hong KIM ,  Sang Yong YOON ,  Ki Jun LEE ,  Jung Soo CHUNG ,  Seong Hyeog CHOI

IPC: G06F12/00

CPC classification number: G06F21/00 ,  G06F11/1012 ,  G06F11/108 ,  G06F12/00 ,  G06F12/14 ,  G11C11/00 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418

Abstract: An apparatus and a method for reading from a non-volatile memory whereby soft decision data is used to determine the reliability of hard decision data. The hard decision data read from the non-volatile memory is de-randomized and the soft decision data read from the non-volatile memory is not de-randomized. Using the soft decision data, the hard decision data is decoded.

Abstract translation: 一种用于从非易失性存储器读取的装置和方法，由此使用软判决数据来确定硬判决数据的可靠性。 从非易失性存储器读取的硬判决数据被去随机化，并且从非易失性存储器读取的软判决数据不被去随机化。 使用软判决数据，硬判决数据被解码。

公开(公告)号：US20120020156A1

公开(公告)日：2012-01-26

申请号：US13190913

申请日：2011-07-26

Applicant: Seong Hyeog Choi ,  Hong Rak Son ,  Jun Jin Kong ,  Yong June Kim

Inventor： Seong Hyeog Choi ,  Hong Rak Son ,  Jun Jin Kong ,  Yong June Kim

IPC: G11C16/10

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/10

Abstract: A method of programming multi-level cells included in a spare region, the method including programming first page data and at least one first dummy data in a first multi-level cell; and programming second page data and at least one second dummy data in a second multi-level cell.

Abstract translation: 一种对包含在备用区域中的多级单元进行编程的方法，所述方法包括在第一多级单元中编程第一页数据和至少一个第一虚拟数据; 以及在第二多级单元中编程第二页数据和至少一个第二伪数据。

公开(公告)号：US08004891B2

公开(公告)日：2011-08-23

申请号：US12453964

申请日：2009-05-28

Applicant: Yong June Kim ,  Kyoung Lae Cho ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

Inventor： Yong June Kim ,  Kyoung Lae Cho ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C7/1006

Abstract: Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.

Abstract translation: 示例性实施例可以提供存储器设备和存储器数据编程方法。 根据示例性实施例的存储器件可编码第一数据页以产生至少一个第一码字，并对第二数据页进行编码以产生第二码字。 存储器装置可以利用连续零个数的最大值和连续零数的第二最大值中的至少一个来生成第一码字。 存储器件可以将至少一个第一代码字和至少一个第二代码字编程到多个多位单元。

公开(公告)号：US20110125975A1

公开(公告)日：2011-05-26

申请号：US12944807

申请日：2010-11-12

Applicant: Jaehong KIM ,  Hee-Seok Eun ,  Ki-Jun Lee ,  Yong-June Kim

Inventor： Jaehong KIM ,  Hee-Seok Eun ,  Ki-Jun Lee ,  Yong-June Kim

IPC: G06F12/06 ,  G06F5/00

CPC classification number: G06F12/0607 ,  G06F2212/7208

Abstract: An interleaving apparatus may include a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data, and an output unit configured to output the interleaving data.

Abstract translation: 交错装置可以包括：第一缓冲器单元，被配置为以具有扇区大小的单位缓冲输入数据以产生扇区单元数据;编码单元，被配置为对扇区单元数据进行编码，并且基于编码生成多个奇偶校验码， 第二缓冲器单元，被配置为交织扇区单元数据和奇偶校验码，并且基于交织产生交织数据，第二缓冲单元包括被配置为存储交织数据的多个输出缓冲器，以及输出单元，其被配置为输出交织 数据。

公开(公告)号：US07924624B2

公开(公告)日：2011-04-12

申请号：US12385705

申请日：2009-04-16

Applicant: Jae Hong Kim ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Yong June Kim

Inventor： Jae Hong Kim ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Yong June Kim

IPC: G11C16/06

CPC classification number: G11C16/3454 ,  G11C11/5628 ,  G11C2211/5621

Abstract: Provided are memory devices and memory programming methods. A memory device may include: a multi-bit cell array that includes a plurality of memory cells; a controller that extracts state information of each of the memory cells, divides the plurality of memory cells into a first group and a second group, assigns a first verify voltage to memory cells of the first group and assigns a second verify voltage to memory cells of the second group; and a programming unit that changes a threshold voltage of each memory cell of the first group until the threshold voltage of each memory cell of the first group is greater than or equal to the first verify voltage, and changes a threshold voltage of each memory cell of the second group until the threshold voltage of each memory cell of the second group is greater than or equal to the second verify voltage.

Abstract translation: 提供的是存储器件和存储器编程方法。 存储器设备可以包括：包括多个存储器单元的多位单元阵列; 提取每个存储单元的状态信息的控制器，将多个存储器单元划分成第一组和第二组，将第一验证电压分配给第一组的存储单元，并将第二验证电压分配给存储单元 第二组 以及编程单元，其改变第一组的每个存储单元的阈值电压，直到第一组的每个存储单元的阈值电压大于或等于第一验证电压，并且改变每个存储单元的阈值电压 直到第二组的每个存储单元的阈值电压大于或等于第二验证电压。

公开(公告)号：US07864574B2

公开(公告)日：2011-01-04

申请号：US12453108

申请日：2009-04-29

Applicant: Kyoung Lae Cho ,  Yong June Kim ,  Seung-Hwan Song ,  Jun Jin Kong

Inventor： Kyoung Lae Cho ,  Yong June Kim ,  Seung-Hwan Song ,  Jun Jin Kong

IPC: G11C11/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

Abstract: Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page.

Abstract translation: 提供的是存储器件和存储器编程方法。 存储器件可以包括包括多个多位单元的多位单元阵列，编程单元，被配置为对多个多位单元中的第一数据页进行编程，并编程多位单元中的第二数据页 具有编程的第一数据页的单元，被配置为将多位单元与编程的第一数据页划分为第一组和第二组的第一控制器，以及配置成将每个的第一数据页的目标阈值电压间隔 基于第一读取电压电平和第二数据页面包括在第一组中的多位单元，并且基于第二读取阈值电压电平来设置包括在第二组中的每个多位单元的目标阈值电压间隔，以及 第二个数据页面。

公开(公告)号：US20100306583A1

公开(公告)日：2010-12-02

申请号：US12784683

申请日：2010-05-21

Applicant: Yong-June Kim ,  Junjin Kong ,  Jaehong Kim ,  Han Woong Yoo

Inventor： Yong-June Kim ,  Junjin Kong ,  Jaehong Kim ,  Han Woong Yoo

IPC: G06F11/20

CPC classification number: G11C29/82

Abstract: Memory systems and related defective block management methods are provided. Methods for managing a defective block in a memory device include allocating a defective block when a memory block satisfies a defective block condition. The allocated defective block is cancelled when the allocated defective block satisfies a defective block cancellation condition.

Abstract translation: 提供了存储器系统和相关的有缺陷的块管理方法。 用于管理存储器件中的缺陷块的方法包括当存储器块满足缺陷块状态时分配缺陷块。 当分配的缺陷块满足缺陷块取消条件时，分配的缺陷块被取消。

公开(公告)号：US20100287447A1

公开(公告)日：2010-11-11

申请号：US12773179

申请日：2010-05-04

Applicant: Hee Seok EUN ,  Jae Hong KIM ,  Seung-Hwan SONG ,  Ho-Chul LEE ,  Yong June KIM ,  Han Woong YOO ,  Jun Jin KONG

Inventor： Hee Seok EUN ,  Jae Hong KIM ,  Seung-Hwan SONG ,  Ho-Chul LEE ,  Yong June KIM ,  Han Woong YOO ,  Jun Jin KONG

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/455 ,  G06F11/1068 ,  G11C16/26

Abstract: Provided is a read method for a memory system. The read method determines whether a read data error is correctable. The read method applies a plurality of read operations at a set read voltage level to identify erasure candidates, when the error is uncorrectable. The read method performs erasure decoding using an error correction code or an error detection code for the erasure candidates.

Abstract translation: 提供了一种用于存储器系统的读取方法。 读取方法确定读取数据错误是否可校正。 读取方法以设定的读取电压电平施加多个读取操作以识别擦除候选，当错误是不可校正的。 读取方法使用用于擦除候选的纠错码或错误检测码来执行擦除解码。