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    High-speed selective cache invalidates and write-backs on GPUS
    72.
    发明授权
    High-speed selective cache invalidates and write-backs on GPUS 有权

    公开(公告)号：US10540280B2

    公开(公告)日：2020-01-21

    申请号：US15390080

    申请日：2016-12-23

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Mark Fowler ,  Jimshed Mirza ,  Anthony Asaro

    IPC: G06F12/1009 ,  G06T1/20 ,  G06F12/0804 ,  G06F12/0891

    Abstract: Techniques for performing cache invalidates and write-backs in an accelerated processing device (e.g., a graphics processing device that renders three-dimensional graphics) are disclosed. The techniques involve receiving requests from a “master” (e.g., the central processing unit). The techniques involve invalidating virtual-to-physical address translations in an address translation request. The techniques include splitting up the requests based on whether the requests target virtually or physically tagged caches. Addresses for the portions of a request that target physically tagged caches are translated using invalidated virtual-to-physical address translations for speed. The split up request is processed to generate micro-transactions for individual caches targeted by the request. Micro-transactions for physically and virtually tagged caches are processed in parallel. Once all micro-transactions for a request have been processed, the unit that made the request is notified.

    REGISTER PARTITION AND PROTECTION FOR VIRTUALIZED PROCESSING DEVICE
    74.
    发明申请
    REGISTER PARTITION AND PROTECTION FOR VIRTUALIZED PROCESSING DEVICE 审中-公开

    公开(公告)号：US20190004840A1

    公开(公告)日：2019-01-03

    申请号：US15637810

    申请日：2017-06-29

    Applicant: ATI Technologies ULC

    Inventor： Anthony Asaro ,  Yinan Jiang ,  Kelly Donald Clark Zytaruk

    IPC: G06F9/455 ,  G06F9/48 ,  G06F9/38 ,  G06F21/74 ,  G06F13/372

    Abstract: A register protection mechanism for a virtualized accelerated processing device (“APD”) is disclosed. The mechanism protects registers of the accelerated processing device designated as physical-function-or-virtual-function registers (“PF-or-VF* registers”), which are single architectural instance registers that are shared among different functions that share the APD in a virtualization scheme whereby each function can maintain a different value in these registers. The protection mechanism for these registers comprises comparing the function associated with the memory address specified by a particular register access request to the “currently active” function for the APD and disallowing the register access request if a match does not occur.

    Routing direct memory access requests in a virtualized computing environment
    76.
    发明授权
    Routing direct memory access requests in a virtualized computing environment 有权

    公开(公告)号：US10162765B2

    公开(公告)日：2018-12-25

    申请号：US15491616

    申请日：2017-04-19

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Andrew G. Kegel ,  Anthony Asaro

    IPC: G06F12/02 ,  G06F13/28 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081

    Abstract: A device may receive a direct memory access request that identifies a virtual address. The device may determine whether the virtual address is within a particular range of virtual addresses. The device may selectively perform a first action or a second action based on determining whether the virtual address is within the particular range of virtual addresses. The first action may include causing a first address translation algorithm to be performed to translate the virtual address to a physical address associated with a memory device when the virtual address is not within the particular range of virtual addresses. The second action may include causing a second address translation algorithm to be performed to translate the virtual address to the physical address when the virtual address is within the particular range of virtual addresses. The second address translation algorithm may be different from the first address translation algorithm.

    SILENT ACTIVE PAGE MIGRATION FAULTS
    77.
    发明申请
    SILENT ACTIVE PAGE MIGRATION FAULTS 审中-公开

    公开(公告)号：US20180307414A1

    公开(公告)日：2018-10-25

    申请号：US15495296

    申请日：2017-04-24

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Wade K. Smith ,  Anthony Asaro

    IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/1027

    CPC classification number: G06F3/0604 ,  G06F3/0647 ,  G06F3/0683 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/657 ,  G06F2212/68

    Abstract: Systems, apparatuses, and methods for migrating memory pages are disclosed herein. In response to detecting that a migration of a first page between memory locations is being initiated, a first page table entry (PTE) corresponding to the first page is located and a migration pending indication is stored in the first PTE. In one embodiment, the migration pending indication is encoded in the first PTE by disabling read and write permissions. If a translation request targeting the first PTE is received by the MMU and the translation request corresponds to a read request, a read operation is allowed to the first page. Otherwise, if the translation request corresponds to a write request, a write operation to the first page is blocked and a silent retry request is generated and conveyed to the requesting client.

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