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公开(公告)号：US06236082B1
公开(公告)日：2001-05-22
申请号：US09134480
申请日：1998-08-13
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L27/11553
摘要： The present invention provides a method for forming a shaped floating gate on an integrated circuit substrate. A trench is etched in a surface of the integrated circuit substrate such that a tip is formed. The tip may be defined by a first sidewall that is approximately perpendicular to the surface of the integrated circuit substrate and a second sidewall that is disposed at an angle to the surface of the integrated circuit substrate. A dielectric layer is then formed over the substrate surface and conforming to the trench. Next, a conductive layer is deposited above the dielectric layer such that it fills the trench. The conductive layer is then etched such that a floating gate is defined. A bottom portion of the floating gate is then contained by the trench. The resulting floating gate and semiconductor device includes a dielectric layer disposed above an integrated circuit substrate surface. The substrate surface defines a trench having a tip that may be defined by a first sidewall and a second sidewall. A conductive layer is formed above the dielectric layer such that it fills the trench and defines a floating gate having a tip contained by the trench. In addition, a diffusion region may be disposed in the integrated circuit substrate such that the tip of the floating gate points into the diffusion region.
摘要翻译： 本发明提供一种在集成电路基板上形成成形浮栅的方法。 在集成电路基板的表面中蚀刻沟槽，从而形成尖端。 尖端可以由大致垂直于集成电路基板的表面的第一侧壁和与集成电路基板的表面成角度设置的第二侧壁限定。 然后在衬底表面上形成电介质层并且与沟槽一致。 接下来，在电介质层上方沉积导电层，使其填充沟槽。 然后蚀刻导电层，使得限定浮动栅极。 然后，浮动栅极的底部被沟槽包围。 所得的浮栅和半导体器件包括设置在集成电路衬底表面上方的电介质层。 衬底表面限定了具有可由第一侧壁和第二侧壁限定的尖端的沟槽。 导电层形成在电介质层之上，使得它填充沟槽并且限定具有由沟槽包含的尖端的浮动栅极。 此外，可以在集成电路基板中设置扩散区域，使得浮动栅极的尖端指向扩散区域。
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公开(公告)号：US06229739B1
公开(公告)日：2001-05-08
申请号：US09662504
申请日：2000-09-14
IPC分类号： G11C700
CPC分类号： G11C7/065
摘要： A sense amplifier places a low positive voltage, such as 0.1 to 0.3 volts, on a bit line instead of ground when a memory cell is read by utilizing a current source circuit to output a reference current that biases a Schottky diode. The current source circuit is implemented with a Schottky diode that utilizes the reverse-biased leakage current of the diode to form the reference current. The current source circuit can also be implemented with a current mirror circuit.
摘要翻译： 当通过利用电流源电路读出存储单元以输出偏置肖特基二极管的参考电流时，读出放大器将位置线上的低正电压（例如0.1至0.3伏特）置于地线上而不是接地。 电流源电路用肖特基二极管实现，其利用二极管的反向偏置漏电流形成参考电流。 电流源电路也可以用电流镜电路来实现。
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73.发明授权公开(公告)号：US06190968B1
公开(公告)日：2001-02-20
申请号：US09185893
申请日：1998-11-04
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L29/42336 , H01L29/7885
摘要： A method for forming an electrically-programmable read-only-memory (EPROM) or a flash memory cell is disclosed. The EPROM or flash memory cell provides both source-side and drain-side injection, along with a reduced cell size, by forming the memory cell in a trench. The drain is formed in the top surface of the substrate, the source is formed in the bottom surface of the trench, and the stacked gate is formed over the sidewall of the trench.
摘要翻译： 公开了一种形成电可编程只读存储器（EPROM）或闪存单元的方法。 EPROM或闪存单元通过在沟槽中形成存储单元来提供源极侧和漏极侧注入以及减小的单元尺寸。 漏极形成在衬底的顶表面中，源极形成在沟槽的底表面中，并且堆叠的栅极形成在沟槽的侧壁上。
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公开(公告)号：US06177315B1
公开(公告)日：2001-01-23
申请号：US09321702
申请日：1999-05-28
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： An EEPROM cell having a double-poly memory-transistor stacked-gate structure and a double-poly access-transistor stacked-gate structure is formed in a process that utilizes a thick layer of oxide as an etch stop when the layers of material are etched to form the memory-transistor stacked-gate structure and the access-transistor stacked-gate structure.
摘要翻译： 当材料层被蚀刻时，在使用厚层氧化物作为蚀刻停止层的工艺中形成具有双重多晶硅存储晶体管堆叠栅结构和双多晶硅存取晶体管叠层栅结构的EEPROM单元 以形成存储晶体管堆叠栅结构和存取晶体管堆叠栅结构。
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公开(公告)号：US06169310A
公开(公告)日：2001-01-02
申请号：US09205110
申请日：1998-12-03
IPC分类号： H01L2362
CPC分类号： H01L27/0288
摘要： An ESD protection device for use with an integrated circuit that provides a low impedance resistive path between IC pads (including Vdd and Vss pads) when power to the IC is off, while assuring adequate isolation between the IC pads when the power is on. The device includes a semiconductor substrate (typically a p-type Si substrate) and at least two vertically integrated pinch resistors formed in the semiconductor substrate. Each of the vertically integrated pinch resistors is connected to a common electrical discharge line and to a pad. Each of the vertically integrated pinch resistors includes a deep well region and a first surface well region, both of the second conductivity type (typically n-type). The first surface well region circumscribes the deep well region, thereby forming a narrow channel region of the first conductivity type (e.g. p-type) therebetween. When no potential is applied to the first surface well regions (i.e. power is off), the two vertically integrated pinch resistors connected by the common electrical discharge line provide a low impedance resistive path between the pads for shunting ESD current. When a potential is applied to the first surface well region by the IC power supply (i.e. power is on), however, the width of the narrow channel region is pinched-off due to a potential-produced depletion region in the narrow channel region, thereby isolating the pads from each other. A process for the formation of the ESD protection device involves sequential formation of each of the device regions in a semiconductor substrate.
摘要翻译： 一种与集成电路一起使用的ESD保护装置，当IC通电时，在IC焊盘（包括Vdd和Vss焊盘）之间提供低阻抗阻抗路径，同时在电源打开时确保IC焊盘之间的充分隔离。 该器件包括形成在半导体衬底中的半导体衬底（通常为p型Si衬底）和至少两个垂直集成的夹持电阻器。 每个垂直集成的夹持电阻器连接到公共放电线和焊盘。 每个垂直集成的夹持电阻器包括深阱区域和第二表面阱区域，第二导电类型（通常为n型）。 第一表面阱区域围绕深阱区域，从而在其间形成第一导电类型（例如p型）的窄通道区域。 当没有电位施加到第一表面阱区域（即电源关闭）时，通过公共放电线连接的两个垂直集成的夹持电阻器在焊盘之间提供了阻抗ESD阻抗的低阻抗路径，用于分流ESD电流。 然而，当通过IC电源将电势施加到第一表面阱区域（即，电源接通）时，窄通道区域的宽度由于窄沟道区域中的潜在产生的耗尽区而被截断， 从而将焊盘彼此隔离。 用于形成ESD保护装置的方法包括在半导体衬底中顺序地形成每个器件区域。
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76.发明授权Starter current source device with automatic shut-down capability and method for its manufacture 有权具有自动停机功能的起动电流源装置及其制造方法
公开(公告)号：US6078094A
公开(公告)日：2000-06-20
申请号：US196458
申请日：1998-11-19
IPC分类号： H01L27/06 , H01L21/8238 , H01L27/092 , H01L29/80 , H01L29/00
CPC分类号： H01L21/823892 , H01L27/092
摘要： An analog circuit starter current source device with automatic shut-down capability. The device includes a semiconductor substrate (typically p-type) with a deep well region (typically n-type) below its surface, a first surface well region (typically n-type) on the surface of the substrate that circumscribes the deep well region, and a narrow channel region (typically p-type) separating the deep well region from the first surface well region. The device also includes a first contact region for connecting the first surface well region to the analog circuit, and a second contact region for connecting a substrate region above the deep well to the analog circuit. The configuration provides a variable-width vertical resistor current path capable of starting an analog circuit and then being automatically shut-down by application of a potential to the first contact region sufficient to produce a depletion region that pinches-off the narrow channel region. A process for forming the starter current source device is also provided. The process includes first providing a semiconductor substrate (e.g. p-type), then forming a deep well region (e.g. n-type) below its surface. This is followed by the formation of a first surface well region (e.g. n-type) on the surface of the substrate such that the first surface well region circumscribes the deep well region, thereby producing a narrow channel (e.g. p-type) therebetween. Finally, a first contact region is formed on the surface of the first surface well region, while a second contact region is formed on the surface of semiconductor substrate above the deep well region.
摘要翻译： 具有自动关机功能的模拟电路起动器电流源装置。 该器件包括在其表面下方具有深阱区（通常为n型）的半导体衬底（通常为p型），在衬底的表面上限定深阱区的第一表面阱区（通常为n型） 以及将深阱区域与第一表面阱区域分离的窄通道区域（通常为p型）。 该装置还包括用于将第一表面阱区域连接到模拟电路的第一接触区域和用于将深井上方的衬底区域连接到模拟电路的第二接触区域。 该配置提供了可变宽度的垂直电阻器电流路径，其能够启动模拟电路，然后通过向第一接触区域施加足以产生夹紧窄沟道区域的耗尽区域的电势自动关闭。 还提供了一种用于形成起动器电流源装置的工艺。 该方法包括首先提供半导体衬底（例如p型），然后在其表面下方形成深阱区域（例如n型）。 接着在衬底的表面上形成第一表面阱区域（例如n型），使得第一表面阱区域围绕深阱区域，从而在其间产生窄通道（例如p型）。 最后，在第一表面阱区域的表面上形成第一接触区域，而在深阱区域上方的半导体衬底的表面上形成第二接触区域。
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公开(公告)号：US5608250A
公开(公告)日：1997-03-04
申请号：US343016
申请日：1994-11-21
申请人： Alexander Kalnitsky
发明人： Alexander Kalnitsky
IPC分类号： H01L21/8247 , G11C11/39 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： G11C11/39 , H01L29/792 , Y10S257/903 , Y10S438/91 , Y10S438/953
摘要： A semiconductor device is described, incorporating electron traps at the interface between a semiconductor substrate and a gate dielectric layer of an insulated gate field effect transistor, such device being capable of retaining charge in the electron traps for a certain time, allowing volatile memory circuits to be produced wherein each cell occupies only the area required for a single transistor.
摘要翻译： 描述了在半导体衬底和绝缘栅场效应晶体管的栅极电介质层之间的界面处并入电子陷阱的半导体器件，该器件能够在电子陷阱中保持一定时间的电荷，从而允许易失性存储器电路 其中每个单元仅占用单个晶体管所需的面积。
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78.发明授权Contact structure for improving photoresist adhesion on a dielectric layer 失效用于改善介电层上的光致抗蚀剂粘附性的接触结构
公开(公告)号：US5424570A
公开(公告)日：1995-06-13
申请号：US828608
申请日：1992-01-31
IPC分类号： H01L23/532 , H01L29/34
CPC分类号： H01L23/5329 , H01L2924/0002 , Y10S257/90
摘要： A structure is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.
摘要翻译： 提供了一种用于改善光致抗蚀剂层和电介质之间的粘合性的结构，以及根据其形成的集成电路。 在集成电路上形成保形介电层。 在保形电介质层上形成层间电介质层。 掺杂层间电介质层使得掺杂浓度允许层回流，同时部分地抑制掺杂层在掺杂层的上表面处的光致抗蚀剂的粘附。 在掺杂介电层上形成未掺杂的介电层。 在附着于未掺杂的介电层的未掺杂的电介质层上形成并图案化光致抗蚀剂层。 对未掺杂的电介质，层间电介质和共形绝缘层进行蚀刻以形成露出一部分下面的导电区域的开口。
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公开(公告)号：US5410174A
公开(公告)日：1995-04-25
申请号：US102529
申请日：1993-08-04
申请人： Alexander Kalnitsky
发明人： Alexander Kalnitsky
IPC分类号： H01L21/28 , H01L21/302 , H01L21/74 , H01L21/768 , H01L23/485 , H01L29/54
CPC分类号： H01L21/743
摘要： A method is provided for forming a polysilicon buried contact of an integrated circuit, and an integrated circuit formed according to the same. A field oxide region is formed over a portion of a substrate leaving an exposed active region. An oxide layer is formed over the active region. A first photoresist layer is formed and patterned over the first silicon layer. The first silicon layer is then etched to form an opening therethrough to expose a portion of the oxide layer. The oxide layer is etched through the opening to expose a portion of the substrate. a conductive etch stop layer is formed over the exposed portion of the substrate and the first photoresist layer. The first photoresist layer and the etch stop layer overlying the first photoresist layer are then removed. A second silicon layer is formed over the first silicon layer and the remaining etch stop layer. A second photoresist layer is formed and patterned over the second silicon layer. The first and second silicon layers are then etched to form a conductive structure contacting the exposed portion of the substrate through the etch stop layer.
摘要翻译： 提供一种用于形成集成电路的多晶硅埋入触点的方法和根据该集成电路形成的集成电路。 在衬底的一部分上形成场氧化物区域，留下暴露的有源区。 在有源区上形成氧化物层。 在第一硅层上形成并图案化第一光致抗蚀剂层。 然后蚀刻第一硅层以形成其中的开口以暴露氧化物层的一部分。 通过开口蚀刻氧化物层以暴露基板的一部分。 在衬底和第一光致抗蚀剂层的暴露部分之上形成导电蚀刻停止层。 然后去除覆盖在第一光致抗蚀剂层上的第一光致抗蚀剂层和蚀刻停止层。 在第一硅层和剩余的蚀刻停止层上形成第二硅层。 在第二硅层上形成并图案化第二光致抗蚀剂层。 然后蚀刻第一和第二硅层以形成通过蚀刻停止层接触衬底的暴露部分的导电结构。
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公开(公告)号：US09076577B2
公开(公告)日：2015-07-07
申请号：US13619225
申请日：2012-09-14
摘要： This disclosure relates to a semiconductor device including resistor arrangement including a first resistor electrically connected to a ground voltage and a second resistor in direct physical contact with the first resistor. The second resistor is configured to receive a temperature independent current and the second resistor has thermal properties similar to those of the first resistor. This disclosure also relates to a semiconductor device including a load configured to receive an operating voltage and a voltage source configured to supply the operating voltage. The semiconductor device further includes a resistor arrangement between the load and the voltage source. This disclosure also relates to a method of using a resistor arrangement to calculate an operating current.
摘要翻译： 本公开涉及包括电阻器装置的半导体器件，该电阻器装置包括电连接到接地电压的第一电阻器和与第一电阻器直接物理接触的第二电阻器。 第二电阻器被配置为接收与温度无关的电流，并且第二电阻器具有与第一电阻器类似的热特性。 本公开还涉及包括被配置为接收工作电压的负载和被配置为提供工作电压的电压源的半导体器件。 半导体器件还包括负载和电压源之间的电阻器配置。 本公开还涉及使用电阻器装置来计算工作电流的方法。
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