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    Displays with intra-frame pause
    72.
    发明授权
    Displays with intra-frame pause 有权
    显示帧内暂停

    公开(公告)号：US09557840B2

    公开(公告)日：2017-01-31

    申请号：US14489338

    申请日：2014-09-17

    Applicant: Apple Inc.

    Inventor： Chin-Wei Lin ,  Chun-Yao Huang ,  Shih Chang Chang ,  Szu-Hsien Lee

    IPC: G06F3/041

    CPC classification number: G06F3/0412 ,  G06F3/0416

    Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.

    Abstract translation: 触摸屏显示器可以包括耦合到显示像素阵列的栅极线驱动器电路。 显示器可以具有帧内暂停（IFP）能力，其中可以在一个或多个帧内消隐间隔期间执行触摸或其它操作。 在一种合适的布置中，栅极驱动电路可以包括多个栅极线驱动器段，每个栅驱动器段由单独的栅极起始脉冲激活。 每个栅极起始脉冲只能在IFP间隔结束时释放。 在另一种合适的布置中，虚拟栅极驱动器单元可插入有源栅极驱动器单元中。 栅极输出信号可能在IFP内部传播通过虚拟栅极驱动器单元。 在另一种合适的布置中，每个有源栅极驱动器单元可以设置有缓冲部分，其保护栅极驱动器单元中的至少一些晶体管免受不期望的应力。

    Display With Intraframe Pause Circuitry
    73.
    发明申请
    Display With Intraframe Pause Circuitry 有权
    显示与帧内暂停电路

    公开(公告)号：US20160118011A1

    公开(公告)日：2016-04-28

    申请号：US14520797

    申请日：2014-10-22

    Applicant: Apple Inc.

    Inventor： Kwang Soon Park ,  Chun-Yao Huang ,  Shih Chang Chang

    IPC: G09G3/36 ,  G06F3/041

    CPC classification number: G09G3/3688 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/044 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0294 ,  G09G2310/063 ,  G09G2310/065 ,  G09G2310/08 ,  G09G2320/0209 ,  G11C19/184

    Abstract: A display may have an array of pixels to display images. Gate line driver circuitry may have stages that supply gate line signals. A gate line may be located in each row of the pixels. Each stage may have an output block that produces a respective one of the gate line signals and may have a carry block that separately produces a carry signal that is provided to a later stage in the gate line driver circuitry. A memory may be provided in at least some of the stages to store signals produced by the output blocks during intraframe pausing operations. At the end of an intraframe pause, the stored signals may be used in restarting production of the gate line signals by output blocks in the gate line driver stages. Circuitry may be used to separately reset the output block and suppress carry signal production by the carry block.

    Abstract translation: 显示器可以具有用于显示图像的像素阵列。 栅极线驱动器电路可以具有提供栅极线信号的级。 栅极线可以位于像素的每一行中。 每个级可以具有产生栅极线信号中的相应一个的输出块，并且可以具有分别产生提供给栅极线驱动器电路中的较后级的进位信号的进位块。 可以在至少一些级中提供存储器，以在帧内暂停操作期间存储由输出块产生的信号。 在帧内暂停结束时，存储的信号可以用于通过栅极线驱动器级中的输出块重新开始生成栅极线信号。 可以使用电路来单独复位输出块，并抑制进位块的进位信号产生。

    Display with Low Reflectivity Alignment Structures
    74.
    发明申请
    Display with Low Reflectivity Alignment Structures 有权
    低反射率对准结构的显示

    公开(公告)号：US20160103349A1

    公开(公告)日：2016-04-14

    申请号：US14512677

    申请日：2014-10-13

    Applicant: Apple Inc.

    Inventor： Kwang Soon Park ,  Byung Duk Yang ,  Christopher L. Boitnott ,  Chun-Yao Huang ,  Kuan-Ying Lin ,  Kyung-Wook Kim ,  Mohd Fadzli A. Hassan ,  Shih Chang Chang ,  Supriya Goyal ,  Yong Kwan Kim ,  Yu-Cheng Chen

    IPC: G02F1/1368 ,  G02F1/1335

    CPC classification number: G02F1/133512 ,  G02F1/1309 ,  G02F1/13452 ,  G02F1/13458

    Abstract: A display may have a liquid crystal layer sandwiched between a thin-film transistor layer and a color filter layer. An upper polarizer may be placed on top of the thin-film transistor layer. A lower polarizer may be placed under the color filter layer. Components may be bonded to bond pads on the inner surface of the thin-film transistor layer using anisotropic conductive film. Bond quality may be assessed by probing probe pads that are coupled to the bond pads or by visually inspecting the bond pads through the thin-film transistor layer. Opaque masking material in the inactive area may be provided with openings to accommodate the bond pads. Additional opaque masking material may be placed on the underside of the upper polarizer and on the upper surface of the thin-film transistor layer to block the openings from view following visual inspection.

    Abstract translation: 显示器可以具有夹在薄膜晶体管层和滤色器层之间的液晶层。 上偏振器可以放置在薄膜晶体管层的顶部。 下偏振器可以放置在滤色器层下方。 可以使用各向异性导电膜将部件结合到薄膜晶体管层的内表面上的接合焊盘。 可以通过探测耦合到接合焊盘的探针焊盘或通过目视检查通过薄膜晶体管层的焊盘来评估焊盘质量。 在不活动区域中的不透明掩模材料可以设置有开口以容纳接合焊盘。 附加的不透明掩模材料可以放置在上偏振器的下侧和薄膜晶体管层的上表面上，以在视觉检查之后阻挡开口。

    DEVICES AND METHODS FOR REDUCING POWER CONSUMPTION AND SIZE OF GATE DRIVERS
    76.
    发明申请
    DEVICES AND METHODS FOR REDUCING POWER CONSUMPTION AND SIZE OF GATE DRIVERS 有权
    降低门电机功耗和尺寸的装置和方法

    公开(公告)号：US20150108916A1

    公开(公告)日：2015-04-23

    申请号：US14502856

    申请日：2014-09-30

    Applicant: APPLE INC.

    Inventor： Louis Luh ,  Chun-Yao Huang

    IPC: G09G3/32 ,  G09G3/36

    CPC classification number: G09G3/3677 ,  G09G3/3266 ,  G09G2310/0286 ,  G09G2310/06 ,  G11C19/184 ,  G11C19/28

    Abstract: One gate driver includes an output node configured to be coupled to a gate line and to provide power to the gate line for driving thin-film transistor (TFT) gates of a display. An input node of the gate driver is configured to receive an input signal. The gate driver includes a first field-effect transistor (FET) having a gate, a drain, and a source. The drain may be coupled to the input node and the source may be coupled to the output node. The gate driver also includes a second FET having a gate, a drain, and a source. The drain may be coupled to the input node. The gate driver includes a capacitor having a first end coupled to the gates of the FETs and a second end coupled to the source of the second FET. Using the gate driver power consumption of the display may be reduced.

    Abstract translation: 一个栅极驱动器包括被配置为耦合到栅极线并且向栅极线提供功率以用于驱动显示器的薄膜晶体管（TFT）栅极的输出节点。 栅极驱动器的输入节点被配置为接收输入信号。 栅极驱动器包括具有栅极，漏极和源极的第一场效应晶体管（FET）。 漏极可以耦合到输入节点，并且源可以耦合到输出节点。 栅极驱动器还包括具有栅极，漏极和源极的第二FET。 漏极可以耦合到输入节点。 栅极驱动器包括具有耦合到FET的栅极的第一端和耦合到第二FET的源极的第二端的电容器。 使用门驱动器可以降低显示器的功耗。

    Gate insulator loss free etch-stop oxide thin film transistor
    77.
    发明授权
    Gate insulator loss free etch-stop oxide thin film transistor 有权
    栅极绝缘体无损蚀刻 - 停止氧化物薄膜晶体管

    公开(公告)号：US08823003B2

    公开(公告)日：2014-09-02

    申请号：US13629537

    申请日：2012-09-27

    Applicant: Apple Inc.

    Inventor： Ming-Chin Hung ,  Kyung Wook Kim ,  Young Bae Park ,  Hao-Lin Chiu ,  Chun-Yao Huang ,  Shih Chang Chang

    IPC: H01L29/10 ,  H01L29/786

    CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/786 ,  H01L29/7869

    Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.

    Abstract translation: 提供了制造薄膜晶体管（TFT）的方法。 该方法包括在覆盖栅电极的栅极绝缘体上形成半导体层，以及在半导体层上沉积绝缘体层，以及蚀刻绝缘体层以形成图案化蚀刻停止件，而不会失去栅极绝缘体。 该方法还包括在半导体层和图案化蚀刻停止物上形成源电极和漏电极。 该方法还包括：除了源电极和漏电极之外的半导体层的一部分，使得半导体层的剩余部分在源电极和栅电极的第一重叠区域和第二重叠区域中覆盖栅极绝缘体 的漏电极和栅电极。

    Electronic Device with Variable Refresh Rate Display Driver Circuitry
    78.
    发明申请
    Electronic Device with Variable Refresh Rate Display Driver Circuitry 审中-公开
    具有可变刷新率显示驱动电路的电子设备

    公开(公告)号：US20140225817A1

    公开(公告)日：2014-08-14

    申请号：US14150579

    申请日：2014-01-08

    Applicant: Apple Inc.

    Inventor： Chun-Yao Huang ,  John Z. Zhong ,  Kyung-Wook Kim ,  Ming-Chin Hung ,  Shih-Chang Chang

    IPC: G09G3/36

    CPC classification number: G09G3/3677 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/28

    Abstract: A display may have an array of display pixels. The array may have rows. Each row of the display pixels may receive gate lines signals on a respective gate line. Gate driver circuitry may be used to drive gate line signals onto the gate lines. Each gate line may be coupled to a logic gate in the gate driver circuitry. The logic gates may each be coupled to a respective latch. A termination block in the gate driver circuitry may have a termination block latch and a termination block logic gate. Signal lines may be used to distribute clock signals from display driver circuitry to the logic gates. Respective signal lines may also be used to distribute a pixel charging initiation signal to a latch in the first row of the array and a pixel charging termination signal to the termination block latch.

    Abstract translation: 显示器可以具有显示像素阵列。 数组可能有行。 显示像素的每行可以在相应的栅极线上接收栅极线信号。 栅极驱动器电路可用于将栅极线信号驱动到栅极线上。 每个栅极线可以耦合到栅极驱动器电路中的逻辑门。 逻辑门可以各自耦合到相应的锁存器。 栅极驱动器电路中的端接块可以具有端接块锁存器和终端块逻​​辑门。 信号线可用于将显示驱动器电路的时钟信号分配给逻辑门。 各个信号线也可以用于将像素充电起始信号分配给阵列的第一行中的锁存器，并将像素充电终止信号分配给终端块锁存器。

    Connection to First Metal Layer in Thin Film Transistor Process
    79.
    发明申请
    Connection to First Metal Layer in Thin Film Transistor Process 有权
    连接薄膜晶体管工艺中的第一金属层

    公开(公告)号：US20140084292A1

    公开(公告)日：2014-03-27

    申请号：US13629547

    申请日：2012-09-27

    Applicant: APPLE INC.

    Inventor： Ming-Chin Hung ,  Young Bae Park ,  Chun-Yao Huang ,  Shih Chang Chang ,  John Z. Zhong

    IPC: H01L29/786 ,  H01L21/20

    CPC classification number: H01L29/7869 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606

    Abstract: A method of connecting to a first metal layer in a semiconductor flow process. Disclosed embodiments connect to the first metal layer by etching a first portion of a viahole through an etch stop layer and a gate insulation layer to reach a first metal layer, depositing a second metal layer such that the second metal layer contacts the first metal layer within the viahole, and etching a second portion of the viahole through a first passivation layer and an organic layer to reach the second metal layer.

    Abstract translation: 一种在半导体流程中连接到第一金属层的方法。 公开的实施例通过蚀刻通孔的第一部分通过蚀刻停止层和栅极绝缘层连接到第一金属层，以到达第一金属层，沉积第二金属层，使得第二金属层与第一金属层接触， 所述通孔，并且通过第一钝化层和有机层蚀刻所述通孔的第二部分以到达所述第二金属层。

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