公开(公告)号：US20050215004A1

公开(公告)日：2005-09-29

申请号：US10811657

申请日：2004-03-29

申请人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

发明人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

IPC分类号： H01G4/005 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L23/522 ,  H01L29/06

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.

摘要翻译： 公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。 该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能， 在MIM电容器的制造中。 该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉​​积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

公开(公告)号：US06881622B2

公开(公告)日：2005-04-19

申请号：US10159226

申请日：2002-05-30

申请人： Chi-Hsing Yu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

发明人： Chi-Hsing Yu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/3213 ,  H01L27/108 ,  H01L21/8242

CPC分类号： H01L28/60 ,  H01L21/28525 ,  H01L21/32134 ,  H01L27/10811

摘要： Within a method for fabricating a capacitor structure within a microelectronic fabrication there is formed a capacitor structure comprising a pair of capacitor plate layers separated by a capacitor dielectric layer. Within the method, at least one of the pair of capacitor plates is formed of a doped amorphous silicon material formed incident to isotropic etching within an etchant solution comprising aqueous ammonium hydroxide, without hydrogen peroxide.

摘要翻译： 在微电子制造中制造电容器结构的方法中，形成了包括由电容器介电层隔开的一对电容器板层的电容器结构。 在该方法中，该对电容器板中的至少一个由在不含过氧化氢的含氢氧化铵的蚀刻剂溶液中入射到各向同性蚀刻的掺杂非晶硅材料形成。

公开(公告)号：US06860275B2

公开(公告)日：2005-03-01

申请号：US10290128

申请日：2002-11-07

申请人： Bao-Ru Young ,  Chia-Shiung Tsai

发明人： Bao-Ru Young ,  Chia-Shiung Tsai

IPC分类号： B08B7/00 ,  H01L21/02 ,  H01L21/302 ,  C23F5/00

CPC分类号： H01L21/02063 ,  B08B7/00

摘要： A three-step polymer removal process that reverses the conventional sequence in which polymer is removed. In the preferred embodiment of the present invention the polymer is first removed from the Gas Deposition Table, after this the polymer is stripped from the inner surface of the created contact hole.

摘要翻译： 三步聚合物去除方法，其反转除去聚合物的常规顺序。 在本发明的优选实施方案中，首先从气体沉积台中除去聚合物，然后从所形成的接触孔的内表面剥离聚合物。

公开(公告)号：US06743732B1

公开(公告)日：2004-06-01

申请号：US09769812

申请日：2001-01-26

申请人： Li-Te Lin ,  Li-Chih Chao ,  Chia-Shiung Tsai

发明人： Li-Te Lin ,  Li-Chih Chao ,  Chia-Shiung Tsai

IPC分类号： H01L21302

CPC分类号： H01L21/76811 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76802 ,  H01L21/76813

摘要： A plasma etch process for organic low-k dielectric layers using NH3 only, or NH3/H2 or NH3/H2 gases. A low k dielectric layer is formed over a substrate. A masking pattern is formed over the low k dielectric layer. The masking pattern has an opening. Using the invention's etch process, the low k dielectric layer is etched through the opening using the masking pattern as an etch mask. In a first embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3 gas. In a second embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/H2 gas. In a third embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/N2 gas. The invention's NH3 containing plasma etch etches organic Low k materials unexpectedly fast. The invention's NH3 only etch had a 30 to 80% high etch rate than N2/H2 etches of low-k materials like Silk™.

摘要翻译： 仅使用NH3或NH3 / H2或NH3 / H2气体的有机低k电介质层的等离子体蚀刻工艺。 在衬底上形成低k电介质层。 在低k电介质层上形成掩模图案。 掩模图案具有开口。 使用本发明的蚀刻工艺，使用掩模图案作为蚀刻掩模，通过开口蚀刻低k电介质层。 在第一实施例中，蚀刻工艺包括：通过施加等离子体功率并仅流过NH 3气体来蚀刻低k电介质层。 在第二实施例中，蚀刻工艺包括：通过施加等离子体功率并仅流过NH 3 / H 2气体来蚀刻低k电介质层。 在第三实施例中，蚀刻工艺包括：通过施加等离子体功率并仅流过NH 3 / N 2气体来蚀刻低k电介质层。 本发明的含NH 3的等离子体蚀刻意外地快速蚀刻有机低k材料。 本发明的仅NH3蚀刻具有比Silk TM的低k材料的N 2 / H 2蚀刻高30至80％的高蚀刻速率。

公开(公告)号：US06624018B1

公开(公告)日：2003-09-23

申请号：US09839965

申请日：2001-04-23

申请人： Chih-Hsing Yu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

发明人： Chih-Hsing Yu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

IPC分类号： H01L218242

CPC分类号： H01L28/87 ,  H01L27/0207 ,  H01L27/10817 ,  H01L27/10852

摘要： A process for fabricating an alternate fin type capacitor structure, used to increase capacitor surface area has been developed. The process features the formation of fin shaped, storage node structures, located in fin type capacitor openings, which are in turn defined in a group of composite insulator layers. A first fin type capacitor opening is formed by selectively creating lateral recesses in first type insulator layers, exposed in a first capacitor opening in the composite insulator layers, while an adjacent, second fin type capacitor opening is formed by selectively creating lateral recesses in second type insulator components, exposed in a second capacitor opening located in the same composite insulator layers. Portions of the lateral recesses in the first and second fin type capacitor openings overlay, allowing intertwined or alternate, storage node structures to be realized, thus reducing the space needed for the capacitor structure. The horizontal features of the fin shaped storage node structure, located in the lateral recesses, result in increased capacitor surface area when compared to counterparts fabricated without the lateral recess component.

摘要翻译： 已经开发了用于制造用于增加电容器表面积的替代鳍式电容器结构的工艺。 该方法的特征在于形成翅片形状的存储节点结构，其位于翅片式电容器开口中，其又限定在一组复合绝缘体层中。 第一鳍型电容器开口通过选择性地产生在第一类型绝缘体层中形成的横向凹槽而形成，暴露在复合绝缘体层中的第一电容器开口中，而相邻的第二鳍状电容器开口通过选择性地产生第二类型的横向凹槽而形成 绝缘体部件，暴露在位于同一复合绝缘体层中的第二电容器开口中。 第一和第二鳍式电容器开口中的横向凹部的部分覆盖，允许实现相互缠绕或交替的存储节点结构，从而减少电容器结构所需的空间。 与没有横向凹槽部件的制造商相比，位于横向凹槽中的翅片形储存结构的水平特征导致增加的电容器表面积。

公开(公告)号：US06579791B1

公开(公告)日：2003-06-17

申请号：US10074909

申请日：2002-02-12

申请人： Yeur Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

发明人： Yeur Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

IPC分类号： H01L214763

CPC分类号： H01L21/76808

摘要： A method of fabricating a dual damascene opening, comprising the following sequential steps. A structure having a stop layer formed over a second low-k material layer formed over a stop layer formed over a first low-k material layer is provided. These layers are etched to form a via opening exposing a portion of the structure. A photoresist layer is formed over the second low-k material layer stop layer and filling the via opening. The photoresist layer having a treated upper portion including a central trench pattern area that is wider than, and substantially centered over, the via opening. The treated upper portion of the photoresist layer preventing any effects to the underlying photoresist layer so that the underlying photoresist layer does not deleteriously interact with the first or second low-k material layer. Removing: (1) the central trench pattern area of the upper treated portion of the photoresist and the photoresist under the central trench pattern area a to form a trench pattern opening exposing a portion of the second low-k material layer stop layer under the removed central trench pattern area; and (2) the photoresist layer within the via opening while leaving a portion of the photoresist layer within the via opening overlying the portion of the structure that was exposed by the via opening. Transferring the trench pattern opening to the second low-k material layer stop layer and the second low-k material layer to form a trench substantially centered over the remaining via opening and completing the dual damascene opening.

摘要翻译： 一种制造双镶嵌开口的方法，包括以下顺序步骤。 提供一种具有形成在形成在第一低k材料层上形成的停止层上的第二低k材料层上的停止层的结构。 蚀刻这些层以形成露出结构的一部分的通孔。 在第二低k材料层停止层上形成光致抗蚀剂层并填充通孔。 光致抗蚀剂层具有经处理的上部，其包括中心沟槽图案区域，该中心沟槽图案区域比通孔开口宽，并且基本上居中。 光致抗蚀剂层的经处理的上部防止对下面的光致抗蚀剂层的任何影响，使得下面的光致抗蚀剂层不会与第一或第二低k材料层有害地相互作用。 去除：（1）光致抗蚀剂的上部处理部分的中心沟槽图案区域和在中心沟槽图案区域a下方的光致抗蚀剂，以形成沟槽图形开口，暴露出被去除的第二低k材料层停止层的一部分 中央沟槽图案区; 和（2）通孔开口内的光致抗蚀剂层，同时留下通孔开口内的一部分光致抗蚀剂层，覆盖由通孔开口暴露的结构部分。 将沟槽图案开口转移到第二低k材料层停止层和第二低k材料层，以形成基本上位于剩余通孔开口上方的沟槽，并完成双镶嵌开口。

公开(公告)号：US06566250B1

公开(公告)日：2003-05-20

申请号：US10100429

申请日：2002-03-18

申请人： Yeur-Luen Tu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

发明人： Yeur-Luen Tu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76873

摘要： A method for forming a self-aligned capping layer over a metal filled feature in a multi-layer semiconductor device including providing an anisotropically etched feature included in a substrate; blanket depositing a first barrier layer over the anisotropically etched feature to prevent diffusion of a metal species into the substrate; filling the anisotropically etched feature with a metal to form a metal filled feature substantially filled with metal; planarizing the substrate surface to include forming an exposed surface of the metal filled feature; and, selectively depositing a second barrier layer to cover the exposed surface of the metal filled feature to form a capping layer.

摘要翻译： 一种用于在多层半导体器件中的金属填充特征上形成自对准覆盖层的方法，包括提供包括在衬底中的各向异性蚀刻特征; 在各向异性蚀刻的特征上毯覆盖沉积第一阻挡层以防止金属物质扩散到基底中; 用金属填充各向异性蚀刻的特征以形成充满金属的金属填充特征; 平面化基底表面以包括形成填充金属的特征的暴露表面; 以及选择性地沉积第二阻挡层以覆盖所述金属填充特征的暴露表面以形成覆盖层。

公开(公告)号：US06501120B1

公开(公告)日：2002-12-31

申请号：US10053151

申请日：2002-01-15

申请人： Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

发明人： Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L21/7682 ,  H01L27/10811 ,  H01L28/84 ,  H01L28/90

摘要： Within both: (1) a method for forming a memory cell structure within a semiconductor integrated circuit microelectronic fabrication; and (2) the memory cell structure resulting from the method, there is provided a capacitor structure whose sidewall is separated from a bitline stud layer which is adjacent thereto and extends there above, by an air gap void. The air gap void provides for attenuated bitline to capacitor structure capacitive coupling, and thus enhanced performance of the memory cell structure.

摘要翻译： 在两者中：（1）在半导体集成电路微电子制造中形成存储单元结构的方法; 和（2）由该方法得到的存储单元结构，提供了一个电容器结构，其电容器结构的侧壁与位于其周围的位线柱层分离，并在其上方延伸有气隙空隙。 气隙空隙为衰减位线提供电容结构电容耦合，从而提高存储单元结构的性能。

公开(公告)号：US06271084B1

公开(公告)日：2001-08-07

申请号：US09759912

申请日：2001-01-16

申请人： Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

发明人： Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

IPC分类号： H01L218242

CPC分类号： H01L28/82 ,  H01L21/76838 ,  H01L21/76895 ,  H01L27/10855 ,  H01L27/10894 ,  H01L28/55 ,  H01L28/60

摘要： A process for forming a vertical, metal-insulator-metal (MIM), capacitor structure, for embedded DRAM devices, using a damascene procedure, has been developed. The process features forming a capacitor opening in a composite insulator layer comprised of a overlying insulator stop layer, a low k insulator layer, and an underlying insulator stop layer, with a lateral recess isotropically formed in the low k insulator layer. After formation of a bottom electrode structure in the capacitor opening, a high k insulator layer is deposited followed by the deposition of a conductive layer, completely filling the capacitor opening. A chemical mechanical polishing procedure is then used to remove portions of the conductive layer, and portions of the high k insulator layer, from the top surface of the overlying insulator stop layer, resulting in the formation of the vertical MIM capacitor structure, in the capacitor opening, comprised of: a top electrode structure, defined from the conductive layer; a capacitor dielectric layer, formed from the high k insulator layer; and a bottom electrode structure.

摘要翻译： 已经开发了使用镶嵌程序形成用于嵌入式DRAM器件的垂直金属 - 绝缘体金属（MIM），电容器结构的工艺。 该工艺的特征是在复合绝缘层中形成电容器开口，该复合绝缘层由上覆的绝缘体停止层，低k绝缘体层和下面的绝缘体阻挡层组成，在低k绝缘体层中各向同性地形成有横向凹槽。 在电容器开口中形成底部电极结构之后，沉积高k绝缘体层，随后沉积导电层，完全填充电容器开口。 然后使用化学机械抛光方法从上覆绝缘体停止层的顶表面去除导电层的部分和高k绝缘体层的部分，从而在电容器中形成垂直MIM电容器结构 开口，包括：由导电层限定的顶部电极结构; 由高k绝缘体层形成的电容器电介质层; 和底部电极结构。

公开(公告)号：US06242362B1

公开(公告)日：2001-06-05

申请号：US09366736

申请日：1999-08-04

申请人： Jen-Cheng Liu ,  Huan-Just Lin ,  Chia-Shiung Tsai ,  Yung-Kuan Hsaio

发明人： Jen-Cheng Liu ,  Huan-Just Lin ,  Chia-Shiung Tsai ,  Yung-Kuan Hsaio

IPC分类号： H01L21302

CPC分类号： H01L21/32137 ,  H01L21/32139

摘要： The present invention provides a method of fabricating a vertical hard mask/conductive pattern profile. The process begins by forming a polysilicon or more preferably a polysilicon and silicide conductive layer over a semiconductor substrate. A silicon oxynitride hard mask layer is formed over the conductive layer. The silicon oxynitride hard mask layer is patterned to form a hard mask pattern. The conductive layer is patterned to form a conductive pattern using Cl2/He—O2/N2 etch chemistry, thereby forming a hard mask/conductive pattern profile that is vertical.

摘要翻译： 本发明提供了制造垂直硬掩模/导电图案轮廓的方法。 该过程通过在半导体衬底上形成多晶硅或更优选多晶硅和硅化物导电层开始。 在导电层上形成氧氮化硅硬掩模层。 将氮氧化硅硬掩模层图案化以形成硬掩模图案。 使用Cl 2 / He-O 2 / N 2蚀刻化学法将导电层图案化以形成导电图案，从而形成垂直的硬掩模/导电图案轮廓。