公开(公告)号：US20050164449A1

公开(公告)日：2005-07-28

申请号：US11087134

申请日：2005-03-22

申请人： Chi-Hsing Yu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

发明人： Chi-Hsing Yu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/3213 ,  H01L27/108 ,  H01L21/8242 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/60 ,  H01L21/28525 ,  H01L21/32134 ,  H01L27/10811

摘要： Within a method for fabricating a capacitor structure within a microelectronic fabrication there is formed a capacitor structure comprising a pair of capacitor plate layers separated by a capacitor dielectric layer. Within the method, at least one of the pair of capacitor plates is formed of a doped amorphous silicon material formed incident to isotropic etching within an etchant solution comprising aqueous ammonium hydroxide, without hydrogen peroxide.

摘要翻译： 在微电子制造中制造电容器结构的方法中，形成了包括由电容器介电层隔开的一对电容器板层的电容器结构。 在该方法中，该对电容器板中的至少一个由在不含过氧化氢的含氢氧化铵的蚀刻剂溶液中入射到各向同性蚀刻的掺杂非晶硅材料形成。

公开(公告)号：US06881622B2

公开(公告)日：2005-04-19

申请号：US10159226

申请日：2002-05-30

申请人： Chi-Hsing Yu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

发明人： Chi-Hsing Yu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/3213 ,  H01L27/108 ,  H01L21/8242

CPC分类号： H01L28/60 ,  H01L21/28525 ,  H01L21/32134 ,  H01L27/10811

摘要： Within a method for fabricating a capacitor structure within a microelectronic fabrication there is formed a capacitor structure comprising a pair of capacitor plate layers separated by a capacitor dielectric layer. Within the method, at least one of the pair of capacitor plates is formed of a doped amorphous silicon material formed incident to isotropic etching within an etchant solution comprising aqueous ammonium hydroxide, without hydrogen peroxide.

摘要翻译： 在微电子制造中制造电容器结构的方法中，形成了包括由电容器介电层隔开的一对电容器板层的电容器结构。 在该方法中，该对电容器板中的至少一个由在不含过氧化氢的含氢氧化铵的蚀刻剂溶液中入射到各向同性蚀刻的掺杂非晶硅材料形成。

公开(公告)号：US06555442B1

公开(公告)日：2003-04-29

申请号：US10042075

申请日：2002-01-08

申请人： Chih-Yang Pai ,  Chih-Hsing Yu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

发明人： Chih-Yang Pai ,  Chih-Hsing Yu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

IPC分类号： H01L2176

CPC分类号： H01L21/76235

摘要： A method of fabricating an STI, comprising the following steps. A silicon structure having a pad oxide layer formed thereover is provided. An undoped poly buffer layer is formed over the pad oxide layer. A hard mask layer is formed over the undoped poly buffer layer. The hard mask layer, the undoped poly buffer layer and the pad oxide layer are patterned to form an opening exposing a portion of the silicon structure within an active area. The opening having exposed side walls. Inorganic spacers are formed over the exposed side walls. Using the patterned hard mask layer and the spacers as hard masks, the silicon structure is etched to form an STI opening within the active area. The inorganic spacers are removed exposing the upper corners of the STI opening. Using an oxidation process, a liner oxide layer is formed within the STI opening, over the upper corners of the STI opening and at least the patterned undoped poly buffer layer exposed by the removal of the inorganic spacers. An STI oxide layer is formed over the patterned hard mask layer, filling the liner oxide layer lined STI opening. The STI oxide layer is planarized and the patterned hard mask, the patterned undoped poly buffer layer and the patterned pad oxide layer are removed to fabricate the STI having rounded corners and without substantial divots.

摘要翻译： 一种制造STI的方法，包括以下步骤。 提供了具有形成在其上的衬垫氧化物层的硅结构。 在衬垫氧化物层上形成未掺杂的多晶缓冲层。 在未掺杂的多缓冲层上形成硬掩模层。 将硬掩模层，未掺杂的多晶缓冲层和焊盘氧化物层图案化以形成暴露有源区域内的硅结构的一部分的开口。 开口具有暴露的侧壁。 在暴露的侧壁上形成无机间隔物。 使用图案化的硬掩模层和间隔物作为硬掩模，蚀刻硅结构以在有效区域内形成STI开口。 去除暴露STI开口的上角的无机间隔物。 使用氧化工艺，在STI开口内，在STI开口的上角上形成衬里氧化物层，并且至少通过去除无机间隔物露出图案化的未掺杂多缓冲层。 在图案化的硬掩模层之上形成STI氧化物层，填充衬里氧化物层衬里的STI开口。 将STI氧化物层平坦化，并且去除图案化的硬掩模，图案化的未掺杂多缓冲层和图案化的衬垫氧化物层，以制造具有圆角并且没有实质上的纹理的STI。

公开(公告)号：US06624018B1

公开(公告)日：2003-09-23

申请号：US09839965

申请日：2001-04-23

申请人： Chih-Hsing Yu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

发明人： Chih-Hsing Yu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

IPC分类号： H01L218242

CPC分类号： H01L28/87 ,  H01L27/0207 ,  H01L27/10817 ,  H01L27/10852

摘要： A process for fabricating an alternate fin type capacitor structure, used to increase capacitor surface area has been developed. The process features the formation of fin shaped, storage node structures, located in fin type capacitor openings, which are in turn defined in a group of composite insulator layers. A first fin type capacitor opening is formed by selectively creating lateral recesses in first type insulator layers, exposed in a first capacitor opening in the composite insulator layers, while an adjacent, second fin type capacitor opening is formed by selectively creating lateral recesses in second type insulator components, exposed in a second capacitor opening located in the same composite insulator layers. Portions of the lateral recesses in the first and second fin type capacitor openings overlay, allowing intertwined or alternate, storage node structures to be realized, thus reducing the space needed for the capacitor structure. The horizontal features of the fin shaped storage node structure, located in the lateral recesses, result in increased capacitor surface area when compared to counterparts fabricated without the lateral recess component.

摘要翻译： 已经开发了用于制造用于增加电容器表面积的替代鳍式电容器结构的工艺。 该方法的特征在于形成翅片形状的存储节点结构，其位于翅片式电容器开口中，其又限定在一组复合绝缘体层中。 第一鳍型电容器开口通过选择性地产生在第一类型绝缘体层中形成的横向凹槽而形成，暴露在复合绝缘体层中的第一电容器开口中，而相邻的第二鳍状电容器开口通过选择性地产生第二类型的横向凹槽而形成 绝缘体部件，暴露在位于同一复合绝缘体层中的第二电容器开口中。 第一和第二鳍式电容器开口中的横向凹部的部分覆盖，允许实现相互缠绕或交替的存储节点结构，从而减少电容器结构所需的空间。 与没有横向凹槽部件的制造商相比，位于横向凹槽中的翅片形储存结构的水平特征导致增加的电容器表面积。

公开(公告)号：US06566250B1

公开(公告)日：2003-05-20

申请号：US10100429

申请日：2002-03-18

申请人： Yeur-Luen Tu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

发明人： Yeur-Luen Tu ,  Chih-Yang Pai ,  Chia-Shiung Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76873

摘要： A method for forming a self-aligned capping layer over a metal filled feature in a multi-layer semiconductor device including providing an anisotropically etched feature included in a substrate; blanket depositing a first barrier layer over the anisotropically etched feature to prevent diffusion of a metal species into the substrate; filling the anisotropically etched feature with a metal to form a metal filled feature substantially filled with metal; planarizing the substrate surface to include forming an exposed surface of the metal filled feature; and, selectively depositing a second barrier layer to cover the exposed surface of the metal filled feature to form a capping layer.

摘要翻译： 一种用于在多层半导体器件中的金属填充特征上形成自对准覆盖层的方法，包括提供包括在衬底中的各向异性蚀刻特征; 在各向异性蚀刻的特征上毯覆盖沉积第一阻挡层以防止金属物质扩散到基底中; 用金属填充各向异性蚀刻的特征以形成充满金属的金属填充特征; 平面化基底表面以包括形成填充金属的特征的暴露表面; 以及选择性地沉积第二阻挡层以覆盖所述金属填充特征的暴露表面以形成覆盖层。

公开(公告)号：US20080116496A1

公开(公告)日：2008-05-22

申请号：US11809642

申请日：2007-06-01

申请人： Kuo-Chyuan Tzeng ,  Kuo-Chiang Ting ,  Chen-Jong Wang ,  Min-Hsiung Chiang ,  Chih-Yang Pai

发明人： Kuo-Chyuan Tzeng ,  Kuo-Chiang Ting ,  Chen-Jong Wang ,  Min-Hsiung Chiang ,  Chih-Yang Pai

IPC分类号： H01L27/108

CPC分类号： H01L27/105 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116

摘要： A novel SOC structure and method of making the same are provided. An SOC comprises a logic region, an SRRM and a DRAM region. The storage capacitor in a DRAM cell is formed in the first dielectric layer in an MIM (metal-insulator-metal) configuration, having a large vertical surface area. A butted contact, formed in said first dielectric layer, comprises a bottom portion abutting a first and second conductive region in an SRAM cell, and a vertically aligned top portion coupled to a first metal layer. The top portion has a substantially larger depth than that of the bottom portion, while substantially smaller in size. Forming this SOC structure does not require adding complex, error-prone additional processing steps on an existing CMOS manufacturing process, thus having little impact on the overall SOC product yield.

摘要翻译： 提供了一种新颖的SOC结构及其制造方法。 SOC包括逻辑区域，SRRM和DRAM区域。 金属 - 绝缘体 - 金属）构造中的DRAM单元中的存储电容器形成在第一介电层中，具有大的垂直表面积。 形成在所述第一电介质层中的对接触点包括邻接SRAM单元中的第一和第二导电区域的底部以及耦合到第一金属层的垂直对齐的顶部。 顶部具有比底部大的深度大得多的深度，而其尺寸基本上更小。 形成这种SOC结构不需要在现有的CMOS制造工艺上增加复杂的，容易出错的附加处理步骤，因此对整个SOC产品产量几乎没有影响。

公开(公告)号：US20090051034A1

公开(公告)日：2009-02-26

申请号：US11892103

申请日：2007-08-20

申请人： Chih-Yang Pai ,  Yuan-Hung Liu ,  Michael Kuang ,  Kuo-Ching Huang

发明人： Chih-Yang Pai ,  Yuan-Hung Liu ,  Michael Kuang ,  Kuo-Ching Huang

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L27/10888 ,  H01L21/76844

摘要： A method for forming a semiconductor device is provided. The method includes the following steps. A substrate having a first contact is provided. A layered structure is formed on the substrate. A recess is formed into the layered structure to expose at least a portion of the first contact. A glue layer is formed on the layered structure and the at least a portion of the first contact. The glue layer is removed from the at least a portion of the first contact. A second contact is formed contacting the first contact and the glue layer.

摘要翻译： 提供一种形成半导体器件的方法。 该方法包括以下步骤。 提供具有第一触点的基板。 在基板上形成层状结构。 形成层状结构中的凹部以暴露第一接触件的至少一部分。 在层状结构和第一接触的至少一部分上形成胶层。 胶层从第一接触件的至少一部分去除。 形成接触第一接触和胶层的第二接触。

公开(公告)号：US20080217775A1

公开(公告)日：2008-09-11

申请号：US11714770

申请日：2007-03-07

申请人： Chih-Yang Pai ,  Wen-Chuan Chiang ,  Chung-Yi Yu ,  Yeur-Luen Tu ,  Yuan-Hung Liu ,  Hsiang-Fan Lee ,  Chuan-Jong Wang

发明人： Chih-Yang Pai ,  Wen-Chuan Chiang ,  Chung-Yi Yu ,  Yeur-Luen Tu ,  Yuan-Hung Liu ,  Hsiang-Fan Lee ,  Chuan-Jong Wang

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/76849 ,  H01L27/10855 ,  H01L27/10888

摘要： A method of forming a contact plug of an eDRAM device includes the following steps: forming a tungsten layer with tungsten seam on a dielectric layer to fill a contact hole; removing the tungsten layer from the top surface of the dielectric layer, recessing the tungsten layer in the contact hole to form a recess of about 600˜900 Angstroms in depth below the top surface of the dielectric layer, depositing a conductive layer on the dielectric layer and the recessed tungsten plug to fill the recess; and removing the conductive layer from the top surface of the dielectric layer to form a conductive plug on the recessed tungsten plug in the contact hole.

摘要翻译： 形成eDRAM器件的接触插塞的方法包括以下步骤：在电介质层上形成具有钨接缝的钨层以填充接触孔; 从电介质层的顶表面去除钨层，使接触孔中的钨层凹陷，以在电介质层的顶表面下方深度形成约600〜900埃的凹陷，在电介质层上沉积导电层 和凹入的钨塞填充凹槽; 并且从电介质层的顶表面去除导电层，以在接触孔中的凹入的钨插塞上形成导电插塞。

公开(公告)号：US08643074B2

公开(公告)日：2014-02-04

申请号：US13462427

申请日：2012-05-02

申请人： Chih-Yang Pai ,  Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chung-Yen Chou

发明人： Chih-Yang Pai ,  Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chung-Yen Chou

IPC分类号： H01L27/108

CPC分类号： H01L28/91 ,  H01L21/76832 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53295 ,  H01L27/108 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces.

摘要翻译： 半导体器件包括半导体衬底，设置在半导体衬底中的隔离结构，设置在隔离结构上的导电层，设置在隔离结构上的电容器，电容器包括顶部电极，底部电极和介于 所述顶部电极和所述底部电极以及将所述导电层和所述底部电极电耦合的第一接触件，所述底部电极在至少两个面上基本接合所述第一接触。

公开(公告)号：US20050056885A1

公开(公告)日：2005-03-17

申请号：US10662609

申请日：2003-09-15

申请人： Chih-Yang Pai ,  Min-Hsiung Chiang ,  Chen-Jong Wang ,  Shou-Gwo Wuu

发明人： Chih-Yang Pai ,  Min-Hsiung Chiang ,  Chen-Jong Wang ,  Shou-Gwo Wuu

IPC分类号： H01L21/8239 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L29/76

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/40 ,  Y10S257/903 ,  Y10S257/904

摘要： Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method also allows for some semiconductor devices on a wafer to have a single polysilicon wafer and other devices to have a dual polysilicon layer. In one embodiment, the semiconductor devices are utilized to form a memory device wherein the storage capacitors and transistors located in the cell region are formed with a dual polysilicon layer and devices in the periphery region are formed with a single polysilicon layer.

摘要翻译： 提供了具有双重多晶硅电极的半导体器件和制造方法。 半导体器件包括沉积在第二多晶硅层上的第一多晶硅层。 每个多晶硅层可以单独掺杂。 该方法还允许晶片上的一些半导体器件具有单个多晶硅晶片和其它器件以具有双重多晶硅层。 在一个实施例中，半导体器件用于形成存储器件，其中位于单元区域中的存储电容器和晶体管形成双重多晶硅层，并且外围区域中的器件形成有单个多晶硅层。