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公开(公告)号：US20120292683A1
公开(公告)日：2012-11-22
申请号：US13111580
申请日：2011-05-19
IPC分类号： H01L29/788 , B82Y99/00
CPC分类号： H01L29/7881 , B82Y10/00 , G11C16/0425 , H01L29/42332 , H01L29/66825
摘要： A method of making a non-volatile memory cell includes forming a plurality of discrete storage elements. A tensile dielectric layer is formed among the discrete storage elements and provides lateral tensile stress to the discrete storage elements. A gate is formed over the discrete storage elements.
摘要翻译： 制造非易失性存储单元的方法包括形成多个离散存储元件。 在离散存储元件之间形成拉伸介电层，并向分立存储元件提供横向拉伸应力。 在离散存储元件上形成栅极。
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72.发明申请公开(公告)号：US20120241839A1
公开(公告)日：2012-09-27
申请号：US13448531
申请日：2012-04-17
IPC分类号： H01L27/088
CPC分类号： H01L29/42332 , H01L21/28273 , H01L27/11524 , H01L29/42328 , H01L29/7881
摘要： Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.
摘要翻译： 实施例包括形成为具有控制栅极和选择栅极的分离栅极非易失性存储器单元，其中控制栅极的至少一部分形成在选择栅极上。 在选择栅极和控制栅极之间形成电荷存储层。 选择栅极使用第一导电层和第二导电层形成。 第二导电层形成在第一导电层之上，并且具有比第一导电层更低的电阻率。 在一个实施例中，第一导电层是多晶硅，第二导电层是氮化钛（TiN）。 在另一个实施例中，第二导电层可以是硅化物或其它导电材料，或者具有比第一导电层低的电阻率的导电材料的组合。
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73.发明授权Split-gate non-volatile memory cell having improved overlap tolerance and method therefor 有权分离门非易失性存储单元具有改进的重叠公差及其方法公开(公告)号：US08163615B1
公开(公告)日：2012-04-24
申请号：US13052529
申请日：2011-03-21
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , H01L21/28273 , H01L27/11524 , H01L29/42328 , H01L29/7881
摘要： A method for forming a split-gate non-volatile memory (NVM) cell includes forming a first gate layer over a semiconductor substrate; forming a conductive layer over the first gate layer; patterning the first gate layer and the conductive layer to form a first sidewall, wherein the first sidewall comprises a sidewall of the first gate layer and a sidewall of the conductive layer; forming a first dielectric layer over the conductive layer and the semiconductor substrate, wherein the first dielectric layer overlaps the first sidewall; forming a second gate layer over the first dielectric layer, wherein the second gate layer is formed over the conductive layer and the first gate layer and overlaps the first sidewall; and patterning the first gate layer and the second gate layer to form a first gate and a second gate, respectively, of the split-gate NVM cell, wherein the second gate overlaps the first gate and a portion of the conductive layer remains between the first gate and the second gate.
摘要翻译： 一种分离栅极非易失性存储器（NVM）单元的形成方法包括在半导体衬底上形成第一栅极层; 在所述第一栅极层上形成导电层; 图案化第一栅极层和导电层以形成第一侧壁，其中第一侧壁包括第一栅极层的侧壁和导电层的侧壁; 在所述导电层和所述半导体衬底之上形成第一电介质层，其中所述第一电介质层与所述第一侧壁重叠; 在所述第一介电层上形成第二栅极层，其中所述第二栅极层形成在所述导电层和所述第一栅极层上并与所述第一侧壁重叠; 以及图案化所述第一栅极层和所述第二栅极层，以分别形成所述分裂栅极NVM单元的第一栅极和第二栅极，其中所述第二栅极与所述第一栅极重叠，并且所述导电层的一部分保留在所述第一栅极 门和第二门。
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公开(公告)号：US08048738B1
公开(公告)日：2011-11-01
申请号：US12760313
申请日：2010-04-14
IPC分类号： H01L21/336 , H01L21/4763 , H01L21/461
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42328 , H01L29/42332 , H01L29/66825 , H01L29/7881
摘要： A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.
摘要翻译： 一种形成半导体器件的方法包括在衬底上形成电介质层。 该方法还包括在电介质层上形成选择栅极层。 该方法还包括以第一蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第一部分，其中以第一蚀刻速率蚀刻选择栅极层的步骤包括使用氧化剂至少氧化 在介质层下面的衬底的顶部以形成氧化物层。 该方法还包括以低于第一蚀刻速率的第二蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第二部分，其中以第二蚀刻速率蚀刻选择栅极层的步骤包括仅去除 电介质层的顶部。
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公开(公告)号：US20110256705A1
公开(公告)日：2011-10-20
申请号：US12760313
申请日：2010-04-14
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42328 , H01L29/42332 , H01L29/66825 , H01L29/7881
摘要： A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.
摘要翻译： 一种形成半导体器件的方法包括在衬底上形成电介质层。 该方法还包括在电介质层上形成选择栅极层。 该方法还包括以第一蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第一部分，其中以第一蚀刻速率蚀刻选择栅极层的步骤包括使用氧化剂至少氧化 在介质层下面的衬底的顶部以形成氧化物层。 该方法还包括以低于第一蚀刻速率的第二蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第二部分，其中以第二蚀刻速率蚀刻选择栅极层的步骤包括仅去除 电介质层的顶部。
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公开(公告)号：US20100248466A1
公开(公告)日：2010-09-30
申请号：US12414778
申请日：2009-03-31
IPC分类号： H01L21/28
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42328 , H01L29/7847 , H01L29/7881
摘要： A method of making a semiconductor device on a semiconductor layer includes: forming a gate dielectric over the semiconductor layer; forming a layer of gate material over the gate dielectric; etching the layer of gate material to form a select gate; forming a storage layer that extends over the select gate and over a portion of the semiconductor layer; depositing an amorphous silicon layer over the storage layer; etching the amorphous silicon layer to form a control gate; and annealing the semiconductor device to crystallize the amorphous silicon layer.
摘要翻译： 在半导体层上制造半导体器件的方法包括：在半导体层上形成栅极电介质; 在所述栅极电介质上形成栅极材料层; 蚀刻栅极材料层以形成选择栅极; 形成在所述选择栅极上方和所述半导体层的一部分上方延伸的存储层; 在所述存储层上沉积非晶硅层; 蚀刻非晶硅层以形成控制栅极; 并对半导体器件进行退火以使非晶硅层结晶。
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公开(公告)号：US07799644B2
公开(公告)日：2010-09-21
申请号：US11460782
申请日：2006-07-28
IPC分类号： H01L21/8234 , H01L21/44
CPC分类号： H01L21/823835 , H01L21/823814 , H01L27/0922
摘要： A transistor having a source with higher resistance than its drain is optimal as a pull-up device in a storage circuit. The transistor has a source region having a source implant having a source resistance. The source region is not salicided. A control electrode region is adjacent the source region for controlling electrical conduction of the transistor. A drain region is adjacent the control electrode region and opposite the source region. The drain region has a drain implant that is salicided and has a drain resistance. The source resistance is more than the drain resistance because the source region having a physical property that differs from the drain region.
摘要翻译： 具有比漏极更高电阻的源极的晶体管作为存储电路中的上拉器件是最佳的。 晶体管具有源极区域，源极源极具有源极电阻。 来源地区没有水淹。 控制电极区域与源极区域相邻，用于控制晶体管的导电。 漏极区域与控制电极区域相邻并与源极区域相对。 漏极区域具有被浸没并具有漏极电阻的漏极注入。 源极电阻大于漏极电阻，因为源极区域具有不同于漏极区域的物理性质。
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公开(公告)号：US20100078703A1
公开(公告)日：2010-04-01
申请号：US12241786
申请日：2008-09-30
IPC分类号： H01L29/792 , H01L21/8246 , H01L21/336
CPC分类号： H01L29/66833 , H01L29/42328 , H01L29/42344 , H01L29/66537 , H01L29/66636 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A method is disclosed for making a non-volatile memory cell on a semiconductor substrate. A select gate structure is formed over the substrate. The control gate structure has a sidewall. An epitaxial layer is formed on the substrate in a region adjacent to the sidewall. A charge storage layer is formed over the epitaxial layer. A control gate is formed over the charge storage layer. This allows for in-situ doping of the epitaxial layer under the select gate without requiring counterdoping. It is beneficial to avoid counterdoping because counterdoping reduces charge mobility and increases the difficulty in controlling threshold voltage. Additionally there may be formed a recess in the substrate and the epitaxial layer is formed in the recess, and a halo implant can be performed, prior to forming the epitaxial layer, through the recess into the substrate in the area under the select gate.
摘要翻译： 公开了一种在半导体衬底上制造非易失性存储单元的方法。 选择栅极结构形成在衬底上。 控制栅结构具有侧壁。 在与侧壁相邻的区域中的衬底上形成外延层。 在外延层上形成电荷存储层。 在电荷存储层上形成控制栅极。 这允许在选择栅极下的原位掺杂外延层而不需要反掺杂。 避免反掺杂是有益的，因为反掺杂降低了电荷迁移率并增加了控制阈值电压的难度。 此外，可以在衬底中形成凹部，并且在凹部中形成外延层，并且可以在形成外延层之前通过凹槽进入在选择栅极下方的区域中的衬底中的晕圈注入。
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公开(公告)号：US20090273013A1
公开(公告)日：2009-11-05
申请号：US12112664
申请日：2008-04-30
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L27/11573 , H01L27/11526 , H01L27/11531 , H01L27/11541 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348
摘要： A split-gate memory device has a select gate having a first work function overlying a first portion of a substrate. A control gate having a second work function overlies a second portion of the substrate proximate the first portion. When the majority carriers of the split-gate memory device are electrons, the first work function is greater than the second work function. When the majority carriers of the split-gate memory device are holes, the first work function is less than the second work function. First and second current electrodes in the substrate are separated by a channel that underlies the control gate and select gate. The differing work functions of the control gate and the select gate result in differing threshold voltages for each gate to optimize device performance. For an N-channel device, the select gate is P conductivity and the control gate is N conductivity.
摘要翻译： 分离栅极存储器件具有覆盖衬底的第一部分的具有第一功函数的选择栅极。 具有第二功函数的控制栅极覆盖靠近第一部分的衬底的第二部分。 当分闸存储器件的多数载流子是电子时，第一功函数大于第二功函数。 当分闸门存储器件的多数载体是孔时，第一功函数小于第二功函数。 衬底中的第一和第二电流电极被控制栅极和选择栅极之下的沟道分开。 控制栅极和选择栅极的不同工作功能导致每个栅极的不同阈值电压以优化器件性能。 对于N沟道器件，选择栅极为P电导率，控制栅极为N电导率。
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80.发明申请ELECTRONIC DEVICE INCLUDING A TRANSISTOR STRUCTURE HAVING AN ACTIVE REGION ADJACENT TO A STRESSOR LAYER 有权包括具有活动区域的晶体管结构的电子器件与压力层相邻公开(公告)号：US20080296633A1
公开(公告)日：2008-12-04
申请号：US12180818
申请日：2008-07-28
IPC分类号： H01L27/088
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/045 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/7843
摘要： An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
摘要翻译： 电子器件可以包括第一导电类型的晶体管结构，场隔离区域和覆盖场隔离区域的第一应力类型的层。 例如，晶体管结构可以是p沟道晶体管结构，并且第一应力类型可以是拉伸的，或者晶体管结构可以是n沟道晶体管结构，并且第一应力类型可以是压缩的。 晶体管结构可以包括位于有源区内的沟道区。 有源区域的边缘包括沟道区域和场隔离区域之间的界面。 从顶视图，该层可以包括位于活动区域边缘附近的边缘。 边缘之间的位置关系可以影响晶体管结构的沟道区内的载流子迁移率。
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