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    MULTILAYERED SEMICONDUCTOR WAFER AND PROCESS FOR MANUFACTURING THE SAME
    71.
    发明申请
    MULTILAYERED SEMICONDUCTOR WAFER AND PROCESS FOR MANUFACTURING THE SAME 有权
    多层半导体晶片及其制造方法

    公开(公告)号：US20090321747A1

    公开(公告)日：2009-12-31

    申请号：US12438818

    申请日：2007-08-22

    申请人： Brian Murphy ,  Reinhold Wahlich

    发明人： Brian Murphy ,  Reinhold Wahlich

    IPC分类号： H01L29/24 ,  H01L21/30

    CPC分类号： H01L21/76254

    摘要： The invention relates to a process for manufacturing a multilayered semiconductor wafer comprising a handle wafer (5) and a layer (40) comprising silicon carbide bonded to the handle wafer (5), the process comprising the steps of: a) providing a handle wafer (5), b) providing a donor wafer (1) comprising a donor layer (2) and a remainder (3) of the donor wafer, the donor layer (2) comprising monocrystalline silicon, e) bonding the donor layer (2) of the donor wafer (1) to the handle wafer (5), and f) removing the remainder (3) of the donor wafer in order to expose the donor layer (2) which remains bonded to the handle wafer (5), the process being characterized by further steps of c) implanting carbon ions into the donor layer (2) in order to produce a layer (4) comprising implanted carbon, and d) heat-treating the donor layer (2) comprising the layer (4) comprising implanted carbon in order to form a silicon carbide donor layer (44) in at least part of the donor layer (2). The invention also relates to a multilayered semiconductor wafer comprising a handle wafer (5) and a silicon carbide donor layer (44) which is bonded to the handle wafer (5), wherein the silicon carbide donor layer (44) is free of twins and free of additional silicon carbide polytypes, as determined by X-ray diffraction.

    摘要翻译： 本发明涉及一种用于制造多层半导体晶片的方法，其包括处理晶片（5）和包含结合到所述处理晶片（5）的碳化硅的层（40），所述方法包括以下步骤：a）提供处理晶片 （5），b）提供包括施主晶片的施主层（2）和剩余部分（3）的施主晶片（1），施主层（2）包括单晶硅，e）将施主层（2） 以及f）去除施主晶片的剩余部分（3），以便露出与晶片（5）保持接合的施主层（2），所述施主晶片（1） 方法的特征在于进一步的步骤，c）将碳离子注入施主层（2）以产生包含植入碳的层（4），和d）热处理包含该层（4）的施主层（2） 包括植入碳以便在施主层（2）的至少一部分中形成碳化硅施体层（44）。 本发明还涉及包括处理晶片（5）和结合到处理晶片（5）的碳化硅施体层（44）的多层半导体晶片，其中碳化硅施体层（44）不含双胞胎， 没有额外的碳化硅多型，通过X射线衍射测定。

    Thread synchronization methods and apparatus for managed run-time environments
    72.
    发明授权
    Thread synchronization methods and apparatus for managed run-time environments 失效
    管理运行时环境的线程同步方法和设备

    公开(公告)号：US07610585B2

    公开(公告)日：2009-10-27

    申请号：US10860692

    申请日：2004-06-03

    申请人： Tatiana Shpeisman ,  Ali-Reza Adl-Tabatabai ,  Brian Murphy

    发明人： Tatiana Shpeisman ,  Ali-Reza Adl-Tabatabai ,  Brian Murphy

    IPC分类号： G06F9/46 ,  G06F12/00 ,  G06F17/30

    CPC分类号： G06F9/52 ,  Y10S707/99938

    摘要： Thread synchronization methods and apparatus for managed run-time environments are disclosed. An example method disclosed herein comprises determining a set of locking operations to perform on a lock corresponding to an object, performing an initial locking operation comprising at least one of a balanced synchronization of the lock and an optimistically balanced synchronization of the lock if the initial locking operation is not unbalanced, and, if the initial locking operation is active and comprises the optimistically balanced synchronization, further comprising modifying a state of a pending optimistically balanced release corresponding to the optimistically balanced synchronization if a subsequent locking operation is unbalanced.

    摘要翻译： 公开了用于管理的运行时环境的线程同步方法和装置。 本文公开的示例性方法包括确定一组锁定操作以对对应于对象的锁执行，执行包括锁的平衡同步和锁的乐观平衡同步中的至少一个的初始锁定操作，如果初始锁定 并且如果初始锁定操作是活动的并且包括乐观平衡的同步，则还包括如果随后的锁定操作不平衡，则修改对应于乐观平衡同步的未决乐观平衡释放的状态。

    Semiconductor substrate and process for producing it
    78.
    发明授权
    Semiconductor substrate and process for producing it 失效
    半导体衬底及其制造方法

    公开(公告)号：US07279700B2

    公开(公告)日：2007-10-09

    申请号：US11266164

    申请日：2005-11-03

    申请人： Dirk Dantz ,  Andreas Huber ,  Reinhold Wahlich ,  Brian Murphy

    发明人： Dirk Dantz ,  Andreas Huber ,  Reinhold Wahlich ,  Brian Murphy

    IPC分类号： H01L29/06

    CPC分类号： H01L21/76251 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02658

    摘要： A semiconductor substrate useful as a donor wafer is a single-crystal silicon wafer having a relaxed, single-crystal layer containing silicon and germanium on its surface, the germanium content at the surface of the layer being in the range from 10% by weight to 100% by weight, and a layer of periodically arranged cavities below the surface. The invention also relates to a process for producing this semiconductor substrate and to an sSOI wafer produced from this semiconductor substrate.

    摘要翻译： 可用作施主晶片的半导体衬底是其表面上具有含有硅和锗的松弛的单晶层的单晶硅晶片，该层表面的锗含量在10重量％至 100重量％，以及在表面下面的周期性排列的空腔层。 本发明还涉及一种用于制造该半导体衬底和由该半导体衬底制造的sSOI晶片的方法。

    Attenuated human-bovine chimeric parainfluenza virus (PIV) vaccines
    79.
    发明申请
    Attenuated human-bovine chimeric parainfluenza virus (PIV) vaccines 有权
    减毒的人 - 牛嵌合副流感病毒（PIV）疫苗

    公开(公告)号：US20070134271A1

    公开(公告)日：2007-06-14

    申请号：US10982223

    申请日：2004-11-04

    申请人： Mario Skiadopoulos ,  Peter Collins ,  Brian Murphy ,  Alexander Schmidt

    发明人： Mario Skiadopoulos ,  Peter Collins ,  Brian Murphy ,  Alexander Schmidt

    IPC分类号： A61K39/145 ,  C12N7/00 ,  C07H21/04 ,  C12N15/86

    CPC分类号： C12N7/00 ,  A61K39/12 ,  A61K39/155 ,  A61K2039/5254 ,  A61K2039/5256 ,  A61K2039/543 ,  A61K2039/544 ,  C07K14/005 ,  C12N2760/18622 ,  C12N2760/18634 ,  C12N2760/18643 ,  C12N2760/18661

    摘要： Chimeric human-bovine parainfluenza viruses (PIVs) are infectious and attenuated in humans and other mammals and useful individually or in combination in vaccine formulations for eliciting an anti-PIV immune response. Also provided are isolated polynucleotide molecules and vectors incorporating a chimeric PIV genome or antigenome which includes a partial or complete human or bovine PIV “background” genome or antigenome combined or integrated with one or more heterologous gene(s) or genome segment(s) of a different PIV. Chimeric human-bovine PIV of the invention include a partial or complete “background” PIV genome or antigenome derived from or patterned after a human or bovine PIV virus combined with one or more heterologous gene(s) or genome segment(s) of a different PIV virus to form the human-bovine chimeric PIV genome or antigenome. In certain aspects of the invention, chimeric PIV incorporate a partial or complete human PIV background genome or antigenome combined with one or more heterologous gene(s) or genome segment(s) from a bovine PIV, whereby the resultant chimeric virus is attenuated by virtue of host-range restriction. In alternate embodiments, human-bovine chimeric PIV incorporate a partial or complete bovine PIV background genome or antigenome combined with one or more heterologous gene(s) or genome segment(s) from a human PIV gene that encode a human PIV immunogenic protein, protein domain or epitope, for example encoded by PIV HN and/or F glycoprotein gene(s) or genome segment(s). Human-bovine chimeric PIV of the invention are also useful as vectors for developing vaccines against other pathogens. A variety of additional mutations and nucleotide modifications are provided within the human-bovine chimeric PIV of the invention to yield desired phenotypic and structural effects.

    摘要翻译： 嵌合人 - 牛副流感病毒（PIV）在人类和其他哺乳动物中具有感染性和减毒性，并且在疫苗制剂中单独使用或组合用于引发抗PIV免疫应答。 还提供了分离的多核苷酸分子和掺入嵌合PIV基因组或抗原组的载体，其包括部分或完整的人或牛PIV“背景”基因组或反基因组，其与一个或多个异源基因或基因组片段组合或整合， 不同的PIV。 本发明的嵌合人牛PIV包括部分或完整的“背景”PIV基因组或反义基因组，其衍生自或构图在人或牛PIV病毒与一个或多个异源基因或不同基因组的基因组片段组合 PIV病毒形成人 - 牛嵌合PIV基因组或抗原组。 在本发明的某些方面，嵌合PIV包含与牛PIV的一个或多个异源基因或基因组片段组合的部分或完整的人PIV背景基因组或反向异构体，由此得到的嵌合病毒被减弱 的主机范围限制。 在替代实施方案中，人 - 牛嵌合PIV掺入部分或完整的牛PIV背景基因组或与来自编码人PIV免疫原性蛋白质的蛋白质的人PIV基因的一个或多个异源基因或基因组片段组合的反义基因组 结构域或表位，例如由PIV HN和/或F糖蛋白基因或基因组片段编码。 本发明的人 - 牛嵌合PIV也可用作开发针对其他病原体的疫苗的载体。 在本发明的人 - 牛嵌合PIV内提供了各种另外的突变和核苷酸修饰，以产生所需的表型和结构效果。

    Method of Reducing Disturbs in Non-Volatile Memory
    80.
    发明申请
    Method of Reducing Disturbs in Non-Volatile Memory 有权
    减少非易失性存储器中的干扰的方法

    公开(公告)号：US20070076510A1

    公开(公告)日：2007-04-05

    申请号：US11538521

    申请日：2006-10-04

    申请人： John Mangan ,  Daniel Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker Quader

    发明人： John Mangan ,  Daniel Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker Quader

    IPC分类号： G11C8/00

    CPC分类号： G11C7/12 ,  G11C16/12 ,  G11C16/3427 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/1204

    摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

    摘要翻译： 在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。 提出了减少这些电流的技术。 在第一方面，减少了在字线上同时编程的单元的数量。 在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。 多个单元可以并行编程，但是它们被布置成处于分开的平面中。 这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合 这些。 在第二个互补方面，位线上的电压电平改变的速率是可调节的。 通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。 这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。