公开(公告)号：US20130134490A1

公开(公告)日：2013-05-30

申请号：US13307787

申请日：2011-11-30

申请人： Karen A. Nummy ,  Chengwen Pei ,  Werner A. Rausch ,  Geng Wang

发明人： Karen A. Nummy ,  Chengwen Pei ,  Werner A. Rausch ,  Geng Wang

IPC分类号： H01L29/94 ,  H01L21/8242

CPC分类号： H01L21/4846 ,  H01L21/82 ,  H01L27/10867 ,  H01L29/66181 ,  H01L29/66636 ,  H01L29/945

摘要： A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.

公开(公告)号：US20120171827A1

公开(公告)日：2012-07-05

申请号：US13417900

申请日：2012-03-12

申请人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

发明人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

IPC分类号： H01L21/8242

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/945

摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

摘要翻译： 提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和 内电极 以及位于沟槽电容器上方的半导体器件。 半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。 存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

公开(公告)号：US20120139080A1

公开(公告)日：2012-06-07

申请号：US12959824

申请日：2010-12-03

申请人： Geng Wang ,  Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

发明人： Geng Wang ,  Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

IPC分类号： H01L21/70 ,  H01L21/20

CPC分类号： H01L28/40 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/0649 ,  H01L29/66181

摘要： A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

摘要翻译： 提供一种半导体结构，其包括在基底半导体层上包含外延生长的半导体层的材料堆叠，外延生长的半导体层上的电介质层和存在于电介质层上的上半导体层。 存在从上半导体层通过电介质层延伸到与外延生长的半导体层接触的电容器。 电容器包括存在于沟槽的侧壁上的节点电介质和填充沟槽的至少一部分的上电极。 在从上半导体层通过电介质层和外延半导体层延伸到基底半导体层的掺杂区域的接触沟槽中存在衬底接触。 还提供了通过沟槽的侧壁接触基底半导体层的衬底接触。 还提供了形成上述结构的方法。

公开(公告)号：US20120122315A1

公开(公告)日：2012-05-17

申请号：US12943956

申请日：2010-11-11

申请人： ROGER A. BOOTH, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： ROGER A. BOOTH, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/302 ,  G06F17/50 ,  H01L21/3205

CPC分类号： H01L21/31056 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate.

摘要翻译： 一种方法包括在具有预定间距的基底上形成图案线。 该方法还包括在图案化线的侧壁上形成间隔壁。 该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。 该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。 该方法还包括将图案化线和另一图案化线的图案转移到衬底。

公开(公告)号：US20110272702A1

公开(公告)日：2011-11-10

申请号：US12775532

申请日：2010-05-07

申请人： Oh-jung Kwon ,  Junedong Lee ,  Chengwen Pei ,  Geng Wang

发明人： Oh-jung Kwon ,  Junedong Lee ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L28/82 ,  H01L27/10867 ,  H01L29/66181

摘要： A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.

摘要翻译： 提供了包括手柄衬底，可选的下绝缘体层，掺杂多晶半导体层，上绝缘体层和顶部半导体层的衬底的衬底。 通过顶部半导体层，上部绝缘体层和掺杂多晶半导体层形成深沟槽。 多晶半导体层的暴露的垂直表面被晶体学蚀刻以在深沟槽中形成随机刻面，从而增加深沟槽中的多晶半导体层的总暴露表面积。 沉积节点电介质和至少一种导电材料以填充沟槽并形成构成eDRAM的电容器的掩埋带部分。 可以形成存取晶体管和其它逻辑器件。

公开(公告)号：US20140008756A1

公开(公告)日：2014-01-09

申请号：US13543966

申请日：2012-07-09

申请人： Chengwen Pei ,  Gan Wang

发明人： Chengwen Pei ,  Gan Wang

IPC分类号： H01L21/306 ,  H01L23/34

CPC分类号： H01L23/3677 ,  H01L21/84 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method including providing a silicon-on-insulator (SOI) substrate including a SOI layer, a buried oxide layer, and a base layer; the buried oxide layer is located below the SOI layer and above the base layer, and the buried oxide layer insulates the SOI layer from the base layer; etching a deep trench into the SOI substrate, the deep trench having a sidewall and a bottom, the deep trench extends from a top surface of the SOI layer, through the buried oxide layer, down to a location within the base layer; forming a dielectric liner on the sidewall and the bottom of the deep trench; forming a conductive fill material on top of the dielectric liner and substantially filling the deep trench, the fill material being thermally conductive; and transferring heat from the SOI layer to the base layer via the fill material.

摘要翻译： 一种包括提供包括SOI层，掩埋氧化物层和基底层的绝缘体上硅（SOI）衬底的方法; 掩埋氧化物层位于SOI层的下方并且在基底层之上，并且掩埋氧化层使SOI层与基底层绝缘; 将深沟槽蚀刻到SOI衬底中，深沟槽具有侧壁和底部，深沟槽从SOI层的顶表面延伸穿过掩埋氧化物层到底层内的位置; 在所述深沟槽的侧壁和底部上形成介电衬垫; 在电介质衬垫的顶部上形成导电填充材料并基本上填充深沟槽，填充材料是导热的; 并且通过填充材料将热量从SOI层传递到基底层。

公开(公告)号：US08535544B2

公开(公告)日：2013-09-17

申请号：US12843228

申请日：2010-07-26

申请人： Chengwen Pei ,  Zhengwen Li

发明人： Chengwen Pei ,  Zhengwen Li

IPC分类号： B44C1/22 ,  B82Y40/00

CPC分类号： G01N33/48721 ,  B32B3/266 ,  B81B2201/058 ,  B81B2203/0384 ,  B81C1/00087 ,  C30B33/10 ,  Y10T428/249975

摘要： A method of fabricating a material having nanoscale pores is provided. In one embodiment, the method of fabricating a material having nanoscale pores may include providing a single crystal semiconductor. The single crystal semiconductor layer is then patterned to provide an array of exposed portions of the single crystal semiconductor layer having a width that is equal to the minimum lithographic dimension. The array of exposed portion of the single crystal semiconductor layer is then etched using an etch chemistry having a selectivity for a first crystal plane to a second crystal plane of 100% or greater. The etch process forms single or an array of trapezoid shaped pores, each of the trapezoid shaped pores having a base that with a second width that is less than the minimum lithographic dimension.

摘要翻译： 提供了制造具有纳米尺度孔的材料的方法。 在一个实施例中，制造具有纳米尺度孔的材料的方法可以包括提供单晶半导体。 然后对单晶半导体层进行构图以提供具有等于最小光刻尺寸的宽度的单晶半导体层的暴露部分的阵列。 然后使用具有对第一晶面的选择性至100％或更大的第二晶体面的蚀刻化学品蚀刻单晶半导体层的暴露部分的阵列。 蚀刻工艺形成单个或一组梯形形孔，每个梯形孔具有基部，其具有小于最小光刻尺寸的第二宽度。

公开(公告)号：US20120275208A1

公开(公告)日：2012-11-01

申请号：US13095164

申请日：2011-04-27

申请人： Yan Zun Li ,  Zhengwen Li ,  Chengwen Pei ,  Jian Yu

发明人： Yan Zun Li ,  Zhengwen Li ,  Chengwen Pei ,  Jian Yu

IPC分类号： G11C17/16 ,  H01L21/8238 ,  H01L23/62

CPC分类号： H01L23/62 ,  G11C17/16 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76886 ,  H01L21/823814 ,  H01L21/84 ,  H01L23/5256 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact. The electrical fuse has a link within the substrate electrically interconnecting the anode contact and the cathode contact. The link comprises a semiconductor layer and a silicide layer. The silicide layer extends beyond the anode contact. An opposite end of the silicide layer extends beyond the cathode contact. A silicon germanium region is embedded in the semiconductor layer under the silicide layer, between the anode contact and the cathode contact.

摘要翻译： 电熔丝在半导体衬底的表面上具有阳极接触。 电熔丝在半导体衬底的与阳极接触件间隔开的表面上具有阴极接触。 电熔丝在衬底内具有连接阳极接触件和阴极接触件的连接。 该连接件包括半导体层和硅化物层。 硅化物层延伸超过阳极接触。 硅化物层的另一端延伸超过阴极接触。 在硅化物层之下的阳极接触和阴极接触之间的半导体层中嵌入硅锗区。

公开(公告)号：US20120021204A1

公开(公告)日：2012-01-26

申请号：US12843228

申请日：2010-07-26

申请人： Chengwen Pei ,  Zhengwen Li

发明人： Chengwen Pei ,  Zhengwen Li

IPC分类号： B32B3/26 ,  C23F1/02

CPC分类号： G01N33/48721 ,  B32B3/266 ,  B81B2201/058 ,  B81B2203/0384 ,  B81C1/00087 ,  C30B33/10 ,  Y10T428/249975

摘要： A method of fabricating a material having nanoscale pores is provided. In one embodiment, the method of fabricating a material having nanoscale pores may include providing a single crystal semiconductor. The single crystal semiconductor layer is then patterned to provide an array of exposed portions of the single crystal semiconductor layer having a width that is equal to the minimum lithographic dimension. The array of exposed portion of the single crystal semiconductor layer is then etched using an etch chemistry having a selectivity for a first crystal plane to a second crystal plane of 100% or greater. The etch process forms single or an array of trapezoid shaped pores, each of the trapezoid shaped pores having a base that with a second width that is less than the minimum lithographic dimension.

摘要翻译： 提供了制造具有纳米尺度孔的材料的方法。 在一个实施例中，制造具有纳米尺度孔的材料的方法可以包括提供单晶半导体。 然后对单晶半导体层进行构图以提供具有等于最小光刻尺寸的宽度的单晶半导体层的暴露部分的阵列。 然后使用具有对第一晶面的选择性至100％或更大的第二晶体面的蚀刻化学品蚀刻单晶半导体层的暴露部分的阵列。 蚀刻工艺形成单个或一组梯形形孔，每个梯形孔具有基部，其具有小于最小光刻尺寸的第二宽度。

公开(公告)号：US20100032732A1

公开(公告)日：2010-02-11

申请号：US12187003

申请日：2008-08-06

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei ,  Ravi M. Todi ,  Xiaojun Yu

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei ,  Ravi M. Todi ,  Xiaojun Yu

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L23/525

CPC分类号： H01L23/5252 ,  H01L27/11206 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical antifuse comprising a field effect transistor includes a gate dielectric having two gate dielectric portions. Upon application of electric field across the gate dielectric, the magnitude of the electrical field is locally enhanced at the boundary between the thick and thin gate dielectric portions due to the geometry, thereby allowing programming of the electrical antifuse at a lower supply voltage between the two electrodes, i.e., the body and the gate electrode of the transistor, across the gate dielectric.

摘要翻译： 包括场效应晶体管的电反熔丝包括具有两个栅电介质部分的栅极电介质。 在栅极电介质上施加电场时，由于几何形状，在厚和薄栅介质部分之间的边界处，电场的幅度被局部增强，从而允许在两个电源电压之间的较低电源电压下对电反熔丝进行编程 电极，即晶体管的主体和栅电极，跨过栅极电介质。