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    HIGH-VOLTAGE SILICON-ON-INSULATOR TRANSISTORS AND METHODS OF MANUFACTURING THE SAME
    71.
    发明申请
    HIGH-VOLTAGE SILICON-ON-INSULATOR TRANSISTORS AND METHODS OF MANUFACTURING THE SAME 失效
    高压硅绝缘体晶体管及其制造方法

    公开(公告)号：US20080048263A1

    公开(公告)日：2008-02-28

    申请号：US11929694

    申请日：2007-10-30

    申请人： William Ma ,  Jack Mandelman ,  Carl Radens ,  William Tonti

    发明人： William Ma ,  Jack Mandelman ,  Carl Radens ,  William Tonti

    IPC分类号： H01L29/786

    CPC分类号： H01L29/66772 ,  H01L29/78612 ,  H01L29/78624 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了制造高压晶体管的第一种方法。 第一种方法包括以下步骤：（1）提供包括在绝缘体上硅（SOI）层之下的绝缘体层下面的体硅层的衬底; 以及（2）形成包括SOI层中的晶体管的扩散区域的晶体管节点的一个或多个部分。 晶体管节点的一部分适于将晶体管内的大于约5V的电压减小到小于约3V的电压。提供了许多其它方面。

    E-FUSE AND METHOD FOR FABRICATING E-FUSES INTEGRATING POLYSILICON RESISTOR MASKS
    72.
    发明申请
    E-FUSE AND METHOD FOR FABRICATING E-FUSES INTEGRATING POLYSILICON RESISTOR MASKS 审中-公开
    电子熔丝和电子熔模聚合多晶硅电阻掩模的方法

    公开(公告)号：US20070262413A1

    公开(公告)日：2007-11-15

    申请号：US11382808

    申请日：2006-05-11

    申请人： Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

    发明人： Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An E-fuse and a method for fabricating an E-fuse are provided integrating polysilicon resistor masks. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and the anode silicide formation. A silicide formation is formed on the polysilicon layer with an unsilicided portion extending over a portion of the cathode adjacent the fuse neck. The unsilicided portion substantially prevents current flow in the silicide formation region of the cathode, with electromigration occurring in the fuse neck during fuse programming. The unsilicided portion has a substantially lower series resistance than the series resistance of the fuse neck.

    摘要翻译： 集成了多晶硅电阻掩模的电子熔丝和用于制造电熔丝的方法被提供。 电熔丝包括限定熔丝形状的多晶硅层，其包括阴极，阳极和连接在阴极和阳极硅化物层之间的保险丝颈。 硅化物形成在多晶硅层上形成，其中非硅化部分在靠近熔丝颈部的阴极的一部分上延伸。 非接触部分基本上防止电流在阴极的硅化物形成区域中流动，在保险丝编程期间在保险丝颈部发生电迁移。 非接触部分具有比熔丝颈部的串联电阻显着更低的串联电阻。

    Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof
    73.
    发明申请
    Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof 有权
    具有变宽的宽度区域的电可编程熔丝结构被配置为增强电流拥挤及其制造方法

    公开(公告)号：US20070210413A1

    公开(公告)日：2007-09-13

    申请号：US11372386

    申请日：2006-03-09

    申请人： Roger Booth ,  Jack Mandelman ,  William Tonti

    发明人： Roger Booth ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element. The first terminal portion has a maximum width greater than a maximum width of the fuse element, and the fuse includes a narrowed width region where the first terminal portion and fuse element interface. The narrowed width region extends at least partially into and includes part of the first terminal portion. The width of the first terminal portion in the narrowed region is less than the maximum width of the first terminal portion to enhance current crowding therein. In another implementation, the fuse element includes a restricted width region wherein width of the fuse element is less than the maximum width thereof to enhance current crowding therein, and length of the restricted width region is less than a total length of the fuse element.

    摘要翻译： 提出了电可编程熔丝结构及其制造方法，其中熔丝包括通过细长的熔丝元件互连的第一和第二端部。 第一端子部分具有大于熔丝元件的最大宽度的最大宽度，并且熔丝包括第一端子部分和熔丝元件接合的变窄的宽度区域。 狭窄宽度区域至少部分地延伸并包括第一端子部分的一部分。 变窄区域中的第一端子部分的宽度小于第一端子部分的最大宽度，以增强其中的电流拥挤。 在另一实施方式中，熔丝元件包括限制宽度区域，其中熔丝元件的宽度小于其最大宽度以增强其中的电流拥挤，并且受限宽度区域的长度小于熔丝元件的总长度。

    Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods
    74.
    发明申请
    Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods 审中-公开
    用于制造具有降低的对闩锁敏感性的半导体器件结构和通过该方法形成的半导体器件结构的方法

    公开(公告)号：US20070194403A1

    公开(公告)日：2007-08-23

    申请号：US11360345

    申请日：2006-02-23

    申请人： Ethan Cannon ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jimmy Kontos ,  Jack Mandelman ,  William Tonti

    发明人： Ethan Cannon ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jimmy Kontos ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L21/76

    CPC分类号： H01L27/0921 ,  H01L21/76229 ,  H01L21/823878

    摘要： Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.

    摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体方法和器件结构。 该方法包括在衬底的半导体材料中形成沟槽，其第一侧壁设置在也在衬底的半导体材料中定义的一对掺杂阱之间。 该方法还包括在沟槽中形成蚀刻掩模以部分地掩蔽沟槽的基底，随后去除暴露在部分屏蔽的基底上的衬底的半导体材料，以限定加深沟槽的变窄的第二侧壁。 加深的沟槽填充有介电材料以限定用于内置于掺杂阱中的器件的沟槽隔离区域。 填充沟槽加深的介质材料增强了闩锁抑制。

    Programmable capacitors and methods of using the same
    75.
    发明申请
    Programmable capacitors and methods of using the same 有权
    可编程电容器及其使用方法

    公开(公告)号：US20070188249A1

    公开(公告)日：2007-08-16

    申请号：US11353516

    申请日：2006-02-14

    申请人： Wagdi Abadeer ,  Anthony Bonaccio ,  Jack Mandelman ,  William Tonti ,  Sebastian Ventrone

    发明人： Wagdi Abadeer ,  Anthony Bonaccio ,  Jack Mandelman ,  William Tonti ,  Sebastian Ventrone

    IPC分类号： H03B5/12

    CPC分类号： H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03L7/095 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

    摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种调整半导体器件的电容的方法。 第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在 将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。 提供了许多其他方面。

    Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
    78.
    发明申请
    Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures 有权
    将镶嵌体FinFET和平面器件集成在共同衬底上的半导体结构以及用于形成这种半导体结构的方法

    公开(公告)号：US20070045748A1

    公开(公告)日：2007-03-01

    申请号：US11211956

    申请日：2005-08-25

    申请人： Roger Booth ,  Jack Mandelman ,  William Tonti

    发明人： Roger Booth ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L29/76

    CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

    摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

    摘要翻译： 通过大马士革方法在公共基板上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。 隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。 翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。 围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。

    Crystal imprinting methods for fabricating subsrates with thin active silicon layers
    79.
    发明申请
    Crystal imprinting methods for fabricating subsrates with thin active silicon layers 失效
    用于制造具有薄的有源硅层的次级层的晶体压印方法

    公开(公告)号：US20060286781A1

    公开(公告)日：2006-12-21

    申请号：US11154907

    申请日：2005-06-16

    申请人： Louis Hsu ,  Jack Mandelman ,  William Tonti

    发明人： Louis Hsu ,  Jack Mandelman ,  William Tonti

    IPC分类号： H01L21/00 ,  H01L21/20

    CPC分类号： H01L29/045 ,  H01L21/84 ,  H01L27/1203

    摘要： Methods of forming semiconductor structures characterized by a thin active silicon layer on an insulating substrate by a crystal imprinting or damascene approach. The methods include patterning an insulating layer to define a plurality of apertures, filling the apertures in the patterned insulating layer with amorphous silicon to define a plurality of amorphous silicon features, and re-growing the amorphous silicon features to define a thin active silicon layer consisting of regrown silicon features. The amorphous silicon features may be regrown such that a number have a first crystal orientation and another number have a different second crystal orientation.

    摘要翻译： 通过晶体压印或镶嵌法在绝缘基板上形成由活性硅层薄的特征的半导体结构的方法。 所述方法包括图案化绝缘层以限定多个孔，用非晶硅填充图案化绝缘层中的孔以限定多个非晶硅特征，以及重新生长非晶硅特征以限定薄的有源硅层， 的再生硅特征。 可以重新生长非晶硅特征，使得数量具有第一晶体取向，而另一数目具有不同的第二晶体取向。