公开(公告)号：US20060098365A1

公开(公告)日：2006-05-11

申请号：US11271059

申请日：2005-11-09

Applicant: Richard Harris ,  Francois Hebert

Inventor： Richard Harris ,  Francois Hebert

IPC: H02H9/00

CPC classification number: H02H9/025 ,  H01L27/0266 ,  H01L27/0727 ,  H01L29/808 ,  H02H9/046

Abstract: An apparatus and method for high-voltage transient blocking employing a transient blocking unit (TBU) that has at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device such that a transient alters a bias voltage Vp of the p-channel device and a bias voltage Vn of the n-channel device in concert. Specifically, the bias voltages are altered such that the p-channel device and n-channel device mutually switch off to block the transient. The depletion mode n-channel device employs a set of cascaded low-voltage depletion mode field effect transistors (FETs) such as metal-oxide-silicon field effect transistors (MOSFETs) connected source-to-drain to achieve the desired high-voltage operation of the TBU.

Abstract translation: 一种使用具有与至少一个耗尽型p沟道器件互连的至少一个耗尽型n沟道器件的瞬态阻断单元（TBU）的装置和方法，使得瞬态改变偏置电压V' p沟道器件的SUB> p 和n沟道器件的偏置电压V N n N一致。 具体地，改变偏置电压，使得p沟道器件和n沟道器件相互切断以阻止瞬变。 耗尽型n沟道器件采用一组级联的低压耗尽型场效应晶体管（FET），例如连接源极到漏极的金属氧化物 - 硅场效应晶体管（MOSFET），以实现所需的高电压工作 的TBU。

公开(公告)号：US20060098363A1

公开(公告)日：2006-05-11

申请号：US11130829

申请日：2005-05-17

Applicant: Francois Hebert ,  Richard Harris

Inventor： Francois Hebert ,  Richard Harris

IPC: H02H9/00

CPC classification number: H01L27/0266 ,  H01L27/0727 ,  H02H9/025 ,  H02H9/046

Abstract: A transient blocking unit (TBU) with integrated over-current protection and discrete over-voltage protection. In one example embodiment, the present innovations are embodied as a unit for protecting a circuit from high voltage and high current, comprising a core transient blocking unit with at least one high voltage device wherein the core transient blocking unit is integrated, and wherein the at least one high voltage device is discrete.

Abstract translation: 具有集成过流保护和离散过电压保护的瞬态阻断单元（TBU）。 在一个示例性实施例中，本发明被实施为用于保护电路免受高电压和高电流的单元，其包括具有至少一个高压器件的核心瞬态阻塞单元，其中所述核心瞬态阻塞单元被集成，并且其中， 至少一个高压装置是离散的。

公开(公告)号：US06768173B2

公开(公告)日：2004-07-27

申请号：US10345467

申请日：2003-01-14

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L31113

CPC classification number: H01L21/26513 ,  H01L21/2658 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1083 ,  H01L29/7833

Abstract: A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The implanted dopants diffuse into the epitaxial layer from the substrate during the formation of the epitaxial layer and subsequent heating steps. The implanted dopants increase the doping concentration in a lower portion of the epitaxial layer. The implanted dopants may diffuse father into the epitaxial layer than dopants in the buried layer forming an up-retro well that prevents vertical punch-through at high operating voltages for thin epitaxial layers. In addition, the doping concentration below the gate may be light so that the threshold voltage of the transistor is low. Also, the high voltage transistor of the present invention may be isolated from the substrate and the buried layer, and have symmetrical source and drain regions so that it can be used as a pass transistor.

Abstract translation: 提供与低电压，亚微米CMOS和BiCMOS工艺兼容的高压MOS晶体管。 本发明的高压晶体管在形成外延层之前具有注入到衬底中的掺杂剂。 在形成外延层和随后的加热步骤期间，注入的掺杂剂从衬底扩散到外延层中。 注入的掺杂剂增加外延层下部的掺杂浓度。 注入的掺杂剂可以将掺杂物扩散到外延层中，而不是掩埋层中的掺杂剂，形成上复古阱，从而防止在高工作电压下对薄的外延层进行垂直穿透。 此外，栅极以下的掺杂浓度可以是轻的，使得晶体管的阈值电压低。 此外，本发明的高电压晶体管可以与衬底和掩埋层隔离，并且具有对称的源极和漏极区域，使得其可以用作传输晶体管。

公开(公告)号：US06677210B1

公开(公告)日：2004-01-13

申请号：US10087881

申请日：2002-02-28

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L21336

CPC classification number: H01L29/66659 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: High voltage transistors with high breakdown voltages are provided. These high voltage transistors are formed with graded drain extension regions. The concentration of charge carriers increases farther away from the gate across each drain extension region, causing severe electric fields to be moved away from the gate. Methods and structures of the present invention may be used to increase a transistor's breakdown voltage to the theoretical limit of the device. High voltage transistors with graded extension regions may be p-channel or n-channel MOSFETs.

Abstract translation: 提供具有高击穿电压的高压晶体管。 这些高压晶体管形成有渐变漏极延伸区域。 电荷载流子的浓度越过每个漏极延伸区域越远离栅极，导致严重的电场移动离开栅极。 本发明的方法和结构可用于将晶体管的击穿电压增加到器件的理论极限。 具有分级扩展区域的高压晶体管可以是p沟道或n沟道MOSFET。

公开(公告)号：US06506648B1

公开(公告)日：2003-01-14

申请号：US09145818

申请日：1998-09-02

Applicant: Francois Hebert ,  Szehim Daniel Ng

Inventor： Francois Hebert ,  Szehim Daniel Ng

IPC: H01L21336

CPC classification number: H01L29/66659 ,  H01L21/743 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/7835

Abstract: Methods of fabricating a high power RF lateral diffused MOS transistor (LDMOS) having increased reliability includes fabricating an N-drift region for the drain prior to fabrication of the gate contact and other process steps in fabricating the transistor. The resulting device has reduced adverse affects from hot carrier injection including reduced threshold voltage shift over time and reduced maximum current reduction over time. Linearity of device is maximized along with increased reliability while channel length is reduced.

Abstract translation: 制造具有增加的可靠性的高功率RF侧向扩散MOS晶体管（LDMOS）的方法包括在制造栅极接触之前制造用于漏极的N漂移区域以及制造晶体管的其它工艺步骤。 所得到的器件减少了热载流子注入的不利影响，包括随时间降低的阈值电压偏移和随时间减小的最大电流减小。 器件的线性度随着可靠性的增加而增加，而沟道长度减小。

公开(公告)号：US5912490A

公开(公告)日：1999-06-15

申请号：US905513

申请日：1997-08-04

Applicant: Francois Hebert ,  Daniel Ng

Inventor： Francois Hebert ,  Daniel Ng

IPC: H01L23/552 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/72

CPC classification number: H01L29/7816 ,  H01L23/552 ,  H01L23/585 ,  H01L27/088 ,  H01L29/402 ,  H01L29/7801 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: Gate to drain capacitance in a lateral DMOS and vertical DMOS field effect transistor is minimized by providing a conductive shield plate under the gate and between the gate and the drain of the transistor. In operation, the shield plate is preferably connected to a DC voltage potential and coupled to AC ground for RF power applications. The shield plate is readily fabricated in a conventional polysilicon gate process by adding one additional polysilicon deposition (or other suitable material), one additional mask, and one additional etch step. The shield plate can include a raised portion which provides lateral capacitive isolation between the gate and the drain. Alternatively, a shield contact can be provided above the shield plate and between the gate and drain to provide lateral isolation.

公开(公告)号：US5827762A

公开(公告)日：1998-10-27

申请号：US850603

申请日：1997-05-02

Applicant: Rashid Bashir ,  Francois Hebert ,  Datong Chen

Inventor： Rashid Bashir ,  Francois Hebert ,  Datong Chen

IPC: H01L21/768 ,  H01L21/8238

CPC classification number: H01L21/76886

Abstract: A buried interconnect structure which is stable at the high temperatures involved in BiCMOS, bipolar, and CMOS transistor process flows, and a method of making the same. The interconnect structure is fully insulated and can be used to form stable, doped structures suitable for use as electrodes and gate structures in a CMOS process, or to form low resistance contacts to N or P-type silicon as part of a bipolar process. Because the interconnect structure is buried and fully insulated from surrounding structures, it may be used to form complex, multi-level devices having a minimized geometry and increased circuit density.

Abstract translation: 在BiCMOS，双极和CMOS晶体管工艺流程中涉及的高温下稳定的埋入式互连结构及其制造方法。 互连结构是完全绝缘的，并且可以用于形成适合用作CMOS工艺中的电极和栅极结构的稳定的掺杂结构，或者作为双极工艺的一部分形成作为N型或P型硅的低电阻接触。 因为互连结构被掩埋并且与周围结构完全绝缘，所以它可用于形成具有最小几何形状和增加的电路密度的复杂的多电平器件。

公开(公告)号：US5684319A

公开(公告)日：1997-11-04

申请号：US518785

申请日：1995-08-24

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66712 ,  H01L29/7802

Abstract: A DMOS device structure, and method of manufacturing the same features a self-aligned source and body contact structure which requires no additional masks. Polysilicon spacers are used to form the source region at the periphery of the gate polysilicon. The preferred method of manufacturing uses five masks to produce a discrete DMOS semiconductor chip. An N- epitaxial layer is grown on an N+ substrate. Thick field oxide is grown. A first mask is used to etch an active region. Thin gate oxide is grown. Doped polysilicon is then deposited. A second mask is used to etch the polysilicon, thereby forming the gates. Insulating oxide is grown. A blanket P body implantation is performed. A thermal drive-in step laterally and vertically diffuses the implanted P type impurity throughout body regions. The insulating oxide is etched. A polysilicon layer is deposited and doped. A dry etch leaves polyslicon spacers along the edges of the gates. A P+ body contact implantation is performed, thereby forming body contact regions. A final annealing step causes vertical and lateral out-diffusion of the N type dopant from the N+ spacers down into substrate to form source N+ regions which partially underlie the gate polysilicon. A third mask is used to etch a gate contact area on a segment of the polysilicon above the field oxide. Metal is deposited, and a fourth photoresist mask delineates a gate pad region and a source pad region which also extends over the source contacts. A passivation layer is deposited and etched in the source and gate pad regions using a fifth mask. In another embodiment, a trench DMOS transistor is fabricated using an additional mask to guide a dry etch to "dig" the trenches.

Abstract translation: DMOS器件结构及其制造方法具有不需要附加掩模的自对准源和体接触结构。 多晶硅间隔物用于在栅极多晶硅的外围形成源区。 优选的制造方法使用五个掩模来生产离散的DMOS半导体芯片。 在N +衬底上生长N-外延层。 生长厚场氧化物。 第一掩模用于蚀刻活性区域。 生长薄栅氧化物。 然后沉积掺杂的多晶硅。 使用第二掩模来蚀刻多晶硅，从而形成栅极。 生长绝缘氧化物。 进行毯子P体植入。 热驱动步骤横向和垂直地将注入的P型杂质扩散到整个体区域。 绝缘氧化物被蚀刻。 沉积并掺杂多晶硅层。 干蚀刻沿着门的边缘留下多晶硅间隔物。 进行P +体接触注入，从而形成身体接触区域。 最后的退火步骤使得N型掺杂剂从N +间隔物垂直和侧向向外扩散到衬底中以形成部分位于栅极多晶硅下面的源极N +区域。 第三掩模用于蚀刻场氧化物上方的多晶硅段上的栅极接触面积。 金属被沉积，并且第四光致抗蚀剂掩模描绘了栅极焊盘区域和也在源极触点上延伸的源焊盘区域。 使用第五掩模在源极和栅极焊盘区域中沉积和蚀刻钝化层。 在另一个实施例中，使用附加掩模制造沟槽DMOS晶体管，以引导干式蚀刻以“挖掘”沟槽。

公开(公告)号：US5681776A

公开(公告)日：1997-10-28

申请号：US708359

申请日：1996-09-04

Applicant: Francois Hebert ,  Datong Chen ,  Rashid Bashir

Inventor： Francois Hebert ,  Datong Chen ,  Rashid Bashir

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76227

Abstract: An isolation method for separating active regions on a semiconductor substrate is disclosed. Portions of the substrate not corresponding to the active regions are etched to a predetermined depth. After some oxide, nitride and dielectric deposition steps, a photoresist is patterned on the dielectric material such that the photoresist completely covers the active regions of the substrate and overlaps into the portions of the substrate that are eventually to represent field oxide regions. Any portion of the dielectric, nitride oxide layers that are not covered by the photoresist are removed and a combined step of selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) is performed. The exposed silicon is then oxidizing and the dielectric, nitride and oxide layers are removed from the active regions of the substrate. The semiconductor device is then ready for subsequent processing.

Abstract translation: 公开了一种用于分离半导体衬底上的有源区的隔离方法。 将不对应于活性区域的基板的部分蚀刻到预定深度。 在一些氧化物，氮化物和电介质沉积步骤之后，光致抗蚀剂被图案化在电介质材料上，使得光致抗蚀剂完全覆盖衬底的有源区并且重叠到最终表示场氧化物区域的衬底部分中。 去除未被光致抗蚀剂覆盖的电介质氮氧化物层的任何部分，并执行选择性外延生长（SEG）和外延横向过度生长（ELO）的组合步骤。 然后将暴露的硅氧化，并从衬底的有源区域去除电介质，氮化物和氧化物层。 然后半导体器件准备好用于后续处理。

公开(公告)号：US5581114A

公开(公告)日：1996-12-03

申请号：US482164

申请日：1995-06-07

Applicant: Rashid Bashir ,  Francois Hebert

Inventor： Rashid Bashir ,  Francois Hebert

IPC: H01L21/8249 ,  H01L27/082 ,  H01L27/088 ,  H01L27/102

CPC classification number: H01L21/8249 ,  Y10S148/01 ,  Y10S257/90

Abstract: A bipolar transistor in accordance with the invention includes a polysilicon base contact (607A) which is self-aligned with a polysilicon emitter (303). The polysilicon emitter is formed from a first polysilicon layer overlying an intrinsic base region (502) in a substrate (201). An extrinsic base (504) in the substrate is in contact with the intrinsic base and is self-aligned with a spacer (406) adjacent to the emitter. The polysilicon base contact is formed from a second polysilicon layer (407) in contact with the extrinsic base and overlying the emitter. A second sidewall spacer (508) is formed on the second polysilicon layer on step caused by the emitter. A protective layer (509, 510) formed on portions of the second polysilicon layer protects the base contact when the second spacer and the underlying portion of the second polysilicon layer are removed. The separation between the polysilicon base contact and the polysilicon emitter is controlled by the thickness the second polysilicon layer and the thickness of the spacers so that the base contact is self-aligned with a fixed separation from the emitter. Layer and spacer thicknesses define separation between the emitter and the base contact and permit sub-micron active regions in the substrate.

Abstract translation: 根据本发明的双极晶体管包括与多晶硅发射器（303）自对准的多晶硅基极接触（607A）。 多晶硅发射体由覆盖衬底（201）中的本征基极区（502）的第一多晶硅层形成。 衬底中的外在基极（504）与本征基极接触并且与邻近发射极的间隔物（406）自对准。 多晶硅基极接触由与外部基极接触并覆盖发射极的第二多晶硅层（407）形成。 第二侧壁间隔物（508）由发射极引起的步骤形成在第二多晶硅层上。 形成在第二多晶硅层的部分上的保护层（509,510）在第二间隔物和第二多晶硅层的下面部分被去除时保护基极接触。 多晶硅基底触点和多晶硅发射极之间的间隔由第二多晶硅层的厚度和间隔物的厚度来控制，使得基极接触件与发射极的固定分离自对准。 层和间隔物厚度限定了发射极和基极接触之间的间隔，并允许衬底中的亚微米有源区。