公开(公告)号：US06506648B1

公开(公告)日：2003-01-14

申请号：US09145818

申请日：1998-09-02

Applicant: Francois Hebert ,  Szehim Daniel Ng

Inventor： Francois Hebert ,  Szehim Daniel Ng

IPC: H01L21336

CPC classification number: H01L29/66659 ,  H01L21/743 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/7835

Abstract: Methods of fabricating a high power RF lateral diffused MOS transistor (LDMOS) having increased reliability includes fabricating an N-drift region for the drain prior to fabrication of the gate contact and other process steps in fabricating the transistor. The resulting device has reduced adverse affects from hot carrier injection including reduced threshold voltage shift over time and reduced maximum current reduction over time. Linearity of device is maximized along with increased reliability while channel length is reduced.

Abstract translation: 制造具有增加的可靠性的高功率RF侧向扩散MOS晶体管（LDMOS）的方法包括在制造栅极接触之前制造用于漏极的N漂移区域以及制造晶体管的其它工艺步骤。 所得到的器件减少了热载流子注入的不利影响，包括随时间降低的阈值电压偏移和随时间减小的最大电流减小。 器件的线性度随着可靠性的增加而增加，而沟道长度减小。

公开(公告)号：US09257525B2

公开(公告)日：2016-02-09

申请号：US13283139

申请日：2011-10-27

Applicant: I-Shan Sun ,  Rick Carlton Jerome ,  Francois Hebert

Inventor： I-Shan Sun ,  Rick Carlton Jerome ,  Francois Hebert

IPC: H01L21/00 ,  H01L29/66 ,  H01L23/48 ,  H01L23/535 ,  H01L21/74 ,  H01L27/06

CPC classification number: H01L29/66204 ,  H01L21/743 ,  H01L23/481 ,  H01L23/535 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for through active-silicon via integration is provided. The method comprises forming an electrical device in a handle wafer. The method also comprises forming an isolation layer over the handle wafer and the electrical device and joining an active layer to the isolation layer. Further, the method comprises forming at least one trench through the active layer and the isolation layer to expose a portion of the handle wafer and depositing an electrically conductive material in the at least one trench, the electrically conductive material providing an electrical connection to the electrical device through the active layer.

Abstract translation: 提供了一种通过积分硅通过集成的方法。 该方法包括在处理晶片中形成电气装置。 该方法还包括在手柄晶片和电气装置上形成隔离层，并将活性层连接到隔离层。 此外，该方法包括通过有源层和隔离层形成至少一个沟槽，以暴露处理晶片的一部分并在至少一个沟槽中沉积导电材料，导电材料提供与电 设备通过活动层。

公开(公告)号：US09209173B2

公开(公告)日：2015-12-08

申请号：US13415384

申请日：2012-03-08

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H02M7/00

CPC classification number: H01L27/088 ,  H01L21/26513 ,  H01L21/823437 ,  H01L21/823487 ,  H01L23/535 ,  H01L23/62 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/30107 ,  H01L2924/3025 ,  H02M7/003 ,  H01L2924/00

Abstract: A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.

Abstract translation: 电压转换器包括具有可以形成在单个管芯（“PowerDie”）上的高侧器件和低侧器件的输出电路。 高侧器件可以包括横向扩散金属氧化物半导体（LDMOS），而低侧器件可以包括沟槽栅极垂直扩散金属氧化物半导体（VDMOS）。 电压转换器还可以包括在不同管芯上的控制器电路，其可以电耦合到输出电路并与输出电路共同封装。

公开(公告)号：US20120098090A1

公开(公告)日：2012-04-26

申请号：US13069789

申请日：2011-03-23

Applicant: Francois Hebert ,  Shea Petricek ,  Nikhil Kelkar

Inventor： Francois Hebert ,  Shea Petricek ,  Nikhil Kelkar

IPC: H01L29/92 ,  H01L21/56

CPC classification number: H01L23/49589 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/16265 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/3718 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48265 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01056 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A power converter device comprises a substrate, a power die mounted on the substrate, and a capacitor die mounted over the power die in a stacked configuration. The capacitor die is electrically coupled to the power die. A packaging material encapsulates the power die and the capacitor die. An integrated circuit die can also be mounted to the substrate and electrically coupled to the power die to receive power signals from the power die, with the packaging material also encapsulating the integrated circuit die.

Abstract translation: 功率转换器装置包括衬底，安装在衬底上的功率管芯和以堆叠构造安装在功率管芯上的电容器管芯。 电容器管芯电耦合到功率管芯。 封装材料封装了电源管芯和电容器管芯。 集成电路管芯也可以安装到衬底上并且电耦合到功率管芯以从功率管芯接收功率信号，封装材料也封装集成电路管芯。

公开(公告)号：US20120007097A1

公开(公告)日：2012-01-12

申请号：US12944163

申请日：2010-11-11

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L29/20 ,  H01L29/872 ,  H01L21/329

CPC classification number: H01L29/872 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66143

Abstract: A Schottky diode comprising a merged guard ring and field plate defining a Schottky contact region is provided. A Schottky metal is formed over at least partially over the Schottky contact region and at least partially over the merged guard ring and field plate.

Abstract translation: 提供了包括合并的保护环和限定肖特基接触区域的场板的肖特基二极管。 肖特基金属至少部分地形成在肖特基接触区域上并且至少部分地在合并的保护环和场板上形成。

公开(公告)号：US20110107589A1

公开(公告)日：2011-05-12

申请号：US13007551

申请日：2011-01-14

Applicant: Francois Hebert ,  Tao Feng ,  Jun Lu

Inventor： Francois Hebert ,  Tao Feng ,  Jun Lu

IPC: H01F7/06

CPC classification number: H01F17/0033 ,  H01F1/344 ,  H01F41/046 ,  H01F2017/002 ,  Y10T29/4902

Abstract: An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.

Abstract translation: 电感器可以包括平面铁氧体磁芯。 第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。 在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。 第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。 第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。 每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。 导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。

公开(公告)号：US20090322461A1

公开(公告)日：2009-12-31

申请号：US12165423

申请日：2008-06-30

Applicant: Francois Hebert ,  Tao Feng ,  Jun Lu

Inventor： Francois Hebert ,  Tao Feng ,  Jun Lu

IPC: H01F27/02

CPC classification number: H01F17/0033 ,  H01F1/344 ,  H01F41/046 ,  H01F2017/002 ,  Y10T29/4902

Abstract: An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.

Abstract translation: 电感器可以包括平面铁氧体磁芯。 第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。 在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。 第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。 第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。 每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。 导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。

公开(公告)号：US20090194880A1

公开(公告)日：2009-08-06

申请号：US12023921

申请日：2008-01-31

Applicant: Tao Feng ,  Francois Hebert ,  Ming Sun ,  Yueh-Se Ho

Inventor： Tao Feng ,  Francois Hebert ,  Ming Sun ,  Yueh-Se Ho

IPC: H01L23/48 ,  H01L21/304

CPC classification number: H01L29/7827 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/81 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/49 ,  H01L29/7802 ,  H01L2224/02371 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

Abstract: Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.

Abstract translation: 封装了功率晶圆级芯片级封装（CSP）和制造工艺。 功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，方便用焊膏安装到印刷电路板（PCB）。

公开(公告)号：US20090114949A1

公开(公告)日：2009-05-07

申请号：US11934040

申请日：2007-11-01

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L29/778 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66734

Abstract: High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility vertical trench DMOSFET may comprise silicon germanium (SiGe) that increases the mobility of the charge carriers in the channel region. In some embodiments the channel region may be strained to increase channel charge carriers mobility.

Abstract translation: 公开了高迁移率垂直沟槽DMOSFET及其制造方法。 高迁移率垂直沟槽DMOSFET的源极区，漏极区或沟道区可以包括增加沟道区中电荷载流子迁移率的硅锗（SiGe）。 在一些实施例中，通道区域可能被应变以增加沟道电荷载流子迁移率。

公开(公告)号：US07504676B2

公开(公告)日：2009-03-17

申请号：US11444853

申请日：2006-05-31

Applicant: Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

Inventor： Anup Bhalla ,  Francois Hebert ,  Daniel S. Ng

IPC: H01L29/80

CPC classification number: H01L29/7802 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66712 ,  H01L29/7828

Abstract: This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.