公开(公告)号：US20140319624A1

公开(公告)日：2014-10-30

申请号：US14327712

申请日：2014-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Nam Sung Kim

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a FinFET device involves performing an epitaxial growth process to form a layer of semiconducting material on a semiconducting substrate, wherein a first portion of the layer of semiconducting material will become a fin structure for the FinFET device and wherein a plurality of second portions of the layer of semiconducting material will become source/drain structures of the FinFET device, forming a gate insulation layer around at least a portion of the fin structure and forming a gate electrode above the gate insulation layer.

公开(公告)号：US20140252480A1

公开(公告)日：2014-09-11

申请号：US14283881

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Werner Juengling

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/7853

Abstract: A device includes a plurality of trenches and fins defined in a substantially un-doped layer of semiconducting material, a gate insulation layer positioned on the fins and on the bottom of the trenches, a gate electrode and a device isolation structure. One method disclosed herein involves identifying a top width of each of a plurality of fins and a depth of a plurality of trenches to be formed in a substantially un-doped layer of semiconducting material, wherein, during operation, the device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to the device, performing at least one process operation to define the trenches and fins in the layer of semiconducting material, forming a gate insulation layer on the fins and on a bottom of the trenches and forming a gate electrode above the gate insulation layer.

Abstract translation: 一种器件包括限定在基本上未掺杂的半导体材料层中的多个沟槽和鳍片，位于鳍片上并位于沟槽底部的栅极绝缘层，栅电极和器件隔离结构。 本文公开的一种方法包括识别多个翅片中的每一个的顶部宽度以及要形成在基本上未掺杂的半导体材料层中的多个沟槽的深度，其中，在操作期间，该装置适于在 至少三个可区分的条件，取决于施加到器件的电压，执行至少一个工艺操作以限定半导体材料层中的沟槽和鳍片，在鳍片上和沟槽的底部上形成栅极绝缘层并形成 在栅极绝缘层上方的栅电极。

公开(公告)号：US20140131777A1

公开(公告)日：2014-05-15

申请号：US13677651

申请日：2012-11-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Hoong Shing Wong ,  Min-hwa Chi

IPC: H01L29/78 ,  H01L21/04

CPC classification number: H01L21/04 ,  H01L29/665 ,  H01L29/66795

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a fin over a semiconductor substrate. The method further includes selectively epitaxially growing a silicon-containing material on the fin and providing the fin with a diamond-shaped cross-section and with an upper portion and a lower portion. The lower portion of the fin is covered with a masking layer. Further, a salicide layer is formed on the upper portion of the fin, and the masking layer prevents formation of the salicide layer on the lower portion of the fin.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成翅片。 该方法还包括在翅片上选择性地外延生长含硅材料，并为翅片提供菱形横截面以及上部和下部。 翅片的下部被掩蔽层覆盖。 此外，在翅片的上部形成有自对准硅层，掩模层防止在翅片的下部形成自对准硅化物层。

公开(公告)号：US10347740B2

公开(公告)日：2019-07-09

申请号：US15367366

申请日：2016-12-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Min-hwa Chi ,  Edmund Kenneth Banghart

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16

Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.

公开(公告)号：US10276390B2

公开(公告)日：2019-04-30

申请号：US15097861

申请日：2016-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Meixiong Zhao ,  Kuniko Kikuta

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L29/49 ,  H01L29/40

Abstract: A method of making a transistor for an integrated circuit includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the substrate. The gate trench includes sidewalls, a trench bottom, and a trench centerline extending normally from a center portion of the trench bottom. The dummy gate is removed from the gate trench. A gate dielectric layer is disposed within the gate trench. A gate work-function metal layer is disposed over the gate dielectric layer, the work-function metal layer including a pair of corner regions proximate the trench bottom. An angled implantation process is utilized to implant a work-function tuning species into the corner regions at a tilt angle relative to the trench centerline, the tilt angle being greater than zero.

公开(公告)号：US10243059B2

公开(公告)日：2019-03-26

申请号：US15994614

申请日：2018-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Srikanth Balaji Samavedan ,  Manfred Eller ,  Min-hwa Chi ,  Hui Zang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/308

Abstract: A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance. The resulting semiconductor structure includes a semiconductor substrate with fin(s) thereon, FinFET(s) integral with the fin(s), the FinFET(s) including a gate electrode, a gate liner lining the gate electrode, and air-gap(s) in gate trench(es) of the FinFET(s), reducing parasitic capacitance by at least about 75 percent as compared to no air-gaps.

公开(公告)号：US20180366470A1

公开(公告)日：2018-12-20

申请号：US16114596

申请日：2018-08-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min-hwa Chi ,  Hui Zang

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L23/535

CPC classification number: H01L27/1104 ,  H01L23/535 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: FinFET structures and methods of forming such structures. The FinFET structures including a substrate; at least two gates disposed on the substrate; a plurality of source/drain regions within the substrate adjacent to each of the gates; a dielectric disposed between each gate and the plurality of source/drain regions adjacent to each gate; a dielectric capping layer disposed on a first one of the at least two gates, wherein no dielectric capping layer is disposed on a second one of the at least two gates; and a local interconnect electrically connected to the second one of the at least two gates, wherein the dielectric capping layer disposed on the first one of the at least two gates prevents an electrical connection between the local interconnect and the first one of the at least two gates.

公开(公告)号：US10147496B2

公开(公告)日：2018-12-04

申请号：US15881356

申请日：2018-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Akhilesh Gautam ,  Suresh Uppal ,  Min-hwa Chi

IPC: G11C17/12 ,  G11C17/18 ,  H01L27/112

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

公开(公告)号：US10096604B2

公开(公告)日：2018-10-09

申请号：US15259472

申请日：2016-09-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min-hwa Chi ,  Hui Zang

IPC: H01L27/11 ,  H01L23/535 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: FinFET structures and methods of forming such structures. The FinFET structures including a substrate; at least two gates disposed on the substrate; a plurality of source/drain regions within the substrate adjacent to each of the gates; a dielectric disposed between each gate and the plurality of source/drain regions adjacent to each gate; a dielectric capping layer disposed on a first one of the at least two gates, wherein no dielectric capping layer is disposed on a second one of the at least two gates; and a local interconnect electrically connected to the second one of the at least two gates, wherein the dielectric capping layer disposed on the first one of the at least two gates prevents an electrical connection between the local interconnect and the first one of the at least two gates.

公开(公告)号：US10068766B2

公开(公告)日：2018-09-04

申请号：US15093310

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/3213

Abstract: A method includes, for example, providing a starting semiconductor structure having a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a protective layer over a portion of at least one material line, the at least one protected material line and at least one unprotected material line having a same critical dimension, oxidizing the at least one unprotected material line to increase the critical dimension compared to the first critical dimension of the at least one protected material line, and etching at least a portion of the oxidized unprotected material line so that the etched critical dimension of the at least one etched material line is different from the first critical dimension of the at least one protected material line.