公开(公告)号：US09012986B2

公开(公告)日：2015-04-21

申请号：US14283881

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Werner Juengling

IPC: H01L29/78 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/7853

Abstract: A device includes a plurality of trenches and fins defined in a substantially un-doped layer of semiconducting material, a gate insulation layer positioned on the fins and on the bottom of the trenches, a gate electrode and a device isolation structure. One method disclosed herein involves identifying a top width of each of a plurality of fins and a depth of a plurality of trenches to be formed in a substantially un-doped layer of semiconducting material, wherein, during operation, the device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to the device, performing at least one process operation to define the trenches and fins in the layer of semiconducting material, forming a gate insulation layer on the fins and on a bottom of the trenches and forming a gate electrode above the gate insulation layer.

Abstract translation: 一种器件包括限定在基本上未掺杂的半导体材料层中的多个沟槽和鳍片，位于鳍片上并位于沟槽底部的栅极绝缘层，栅电极和器件隔离结构。 本文公开的一种方法包括识别多个翅片中的每一个的顶部宽度以及要形成在基本上未掺杂的半导体材料层中的多个沟槽的深度，其中，在操作期间，该装置适于在 至少三个可区分的条件，取决于施加到器件的电压，执行至少一个工艺操作以限定半导体材料层中的沟槽和鳍片，在鳍片上和沟槽的底部上形成栅极绝缘层并形成 在栅极绝缘层上方的栅电极。

公开(公告)号：US20140225168A1

公开(公告)日：2014-08-14

申请号：US13764115

申请日：2013-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel T. Pham ,  Werner Juengling ,  William J. Taylor, JR. ,  Robert Miller

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/7846 ,  H01L29/785

Abstract: One method includes forming first and second spaced-apart trenches extending at least partially into a semiconducting substrate defining a fin structure for the device, forming a stress-inducing material having a first type of stress in the first trench, forming a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different than the first type of stress, and forming a gate structure around a portion of the fin structure. One device includes first and second spaced-apart trenches in a semiconducting substrate defining at least a portion of a fin for the device, a stress-inducing material having a first type of stress in the first trench, a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different type than the first stress, and a gate structure around a portion of the fin structure.

Abstract translation: 一种方法包括形成第一和第二间隔开的沟槽，其至少部分延伸到限定用于器件的鳍结构的半导体衬底中，形成在第一沟槽中具有第一类型应力的应力诱导材料，形成第二应力诱导 第二沟槽中的材料，第二应力诱导材料具有不同于第一类型应力的第二应力，以及围绕鳍结构的一部分形成栅极结构。 一个器件包括在半导体衬底中限定用于器件的鳍片的至少一部分的第一和第二间隔开的沟槽，在第一沟槽中具有第一类型应力的应力诱导材料，在第一沟槽中的第二应力诱导材料 第二沟槽，第二应力诱导材料具有与第一应力不同的第二应力，以及围绕鳍结构的一部分的栅极结构。

公开(公告)号：US08772117B2

公开(公告)日：2014-07-08

申请号：US13705261

申请日：2012-12-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Werner Juengling

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/7853

Abstract: A device includes a plurality of trenches and fins defined in a substantially un-doped layer of semiconducting material, a gate insulation layer positioned on the fins and on the bottom of the trenches, a gate electrode and a device isolation structure. One method disclosed herein involves identifying a top width of each of a plurality of fins and a depth of a plurality of trenches to be formed in a substantially un-doped layer of semiconducting material, wherein, during operation, the device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to the device, performing at least one process operation to define the trenches and fins in the layer of semiconducting material, forming a gate insulation layer on the fins and on a bottom of the trenches and forming a gate electrode above the gate insulation layer.

Abstract translation: 一种器件包括限定在基本上未掺杂的半导体材料层中的多个沟槽和鳍片，位于鳍片上并位于沟槽底部的栅极绝缘层，栅电极和器件隔离结构。 本文公开的一种方法包括识别多个翅片中的每一个的顶部宽度以及要形成在基本上未掺杂的半导体材料层中的多个沟槽的深度，其中，在操作期间，该装置适于在 至少三个可区分的条件，取决于施加到器件的电压，执行至少一个工艺操作以限定半导体材料层中的沟槽和鳍片，在鳍片上和沟槽的底部上形成栅极绝缘层并形成 在栅极绝缘层上方的栅电极。

公开(公告)号：US08877588B2

公开(公告)日：2014-11-04

申请号：US13764115

申请日：2013-02-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel T. Pham ,  Werner Juengling ,  William J. Taylor, Jr. ,  Robert Miller

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/7846 ,  H01L29/785

Abstract: One method includes forming first and second spaced-apart trenches extending at least partially into a semiconducting substrate defining a fin structure for the device, forming a stress-inducing material having a first type of stress in the first trench, forming a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different than the first type of stress, and forming a gate structure around a portion of the fin structure. One device includes first and second spaced-apart trenches in a semiconducting substrate defining at least a portion of a fin for the device, a stress-inducing material having a first type of stress in the first trench, a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different type than the first stress, and a gate structure around a portion of the fin structure.

Abstract translation: 一种方法包括形成第一和第二间隔开的沟槽，其至少部分延伸到限定用于器件的鳍结构的半导体衬底中，形成在第一沟槽中具有第一类型应力的应力诱导材料，形成第二应力诱导 第二沟槽中的材料，第二应力诱导材料具有不同于第一类型应力的第二应力，以及围绕鳍结构的一部分形成栅极结构。 一个器件包括在半导体衬底中限定用于器件的鳍片的至少一部分的第一和第二间隔开的沟槽，在第一沟槽中具有第一类型应力的应力诱导材料，在第一沟槽中的第二应力诱导材料 第二沟槽，第二应力诱导材料具有与第一应力不同的第二应力，以及围绕鳍结构的一部分的栅极结构。

公开(公告)号：US20140151807A1

公开(公告)日：2014-06-05

申请号：US13705261

申请日：2012-12-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min-hwa Chi ,  Werner Juengling

IPC: H01L21/84 ,  H01L27/12

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/7853

Abstract: A device includes a plurality of trenches and fins defined in a substantially un-doped layer of semiconducting material, a gate insulation layer positioned on the fins and on the bottom of the trenches, a gate electrode and a device isolation structure. One method disclosed herein involves identifying a top width of each of a plurality of fins and a depth of a plurality of trenches to be formed in a substantially un-doped layer of semiconducting material, wherein, during operation, the device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to the device, performing at least one process operation to define the trenches and fins in the layer of semiconducting material, forming a gate insulation layer on the fins and on a bottom of the trenches and forming a gate electrode above the gate insulation layer.

公开(公告)号：US09087733B2

公开(公告)日：2015-07-21

申请号：US14575677

申请日：2014-12-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Werner Juengling

IPC: H01L21/70 ,  H01L27/11 ,  H01L29/16 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/11 ,  H01L21/76229 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/0684 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method is provided for forming SRAM cells with low energy implants. Embodiments include forming deep trenches in a silicon substrate; forming a deep n-well or deep p-well around a bottom of each deep trench; filling the deep trenches with oxide; forming a first or second shallow trench between each pair of adjacent deep trenches; forming a first p-well or first n-well, respectively, above each deep n-well or p-well; forming a second n-well at a bottom of each first shallow trench; forming a p+ region above each second n-well on each side of each first shallow trench; filling the first shallow trenches with oxide; forming a second p-well at a bottom of each second shallow trench; filling the second shallow trenches with oxide; forming a n+ region above each second p-well on each side of each second shallow trench.

Abstract translation: 提供了一种用于形成具有低能量注入的SRAM单元的方法。 实施例包括在硅衬底中形成深沟槽; 在每个深沟的底部周围形成一个深n井或深p井; 用氧化物填充深沟槽; 在每对相邻的深沟槽之间形成第一或第二浅沟槽; 分别在每个深n阱或p阱之上形成第一个p阱或第一个n阱; 在每个第一浅沟槽的底部形成第二个n阱; 在每个第一浅沟槽的每一侧上形成在每个第二n阱上方的p +区域; 用氧化物填充第一浅沟; 在每个第二浅沟槽的底部形成第二p阱; 用氧化物填充第二浅沟; 在每个第二浅沟槽的每一侧上在每个第二p阱上方形成n +区。

公开(公告)号：US09054212B2

公开(公告)日：2015-06-09

申请号：US13664062

申请日：2012-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Werner Juengling

IPC: H01L21/311 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method and device are provided for etching and replacing silicon fins in connection with a FinFET integration process. Embodiments include providing a first plurality and a second plurality of silicon fins on a silicon wafer with an oxide between adjacent silicon fins; forming a first nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween; etching the second plurality of silicon fins, forming trenches; removing the first nitride liner; depositing a second nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween and in the trenches; removing the second nitride liner down to the upper surface of the first plurality of silicon fins; and recessing the oxide.

Abstract translation: 提供了一种用于蚀刻和替换与FinFET集成工艺相关的硅散热片的方法和装置。 实施例包括在硅晶片上提供在相邻硅散热片之间的氧化物的第一多个和第二多个硅散热片; 在所述第一多个硅散热片的上表面上形成第一氮化物衬垫及其之间的氧化物; 蚀刻第二多个硅散热片，形成沟槽; 去除第一氮化物衬垫; 在所述第一多个硅散热片的上表面上沉积第二氮化物衬垫，以及在所述沟槽中沉积第二氮化物衬垫; 将所述第二氮化物衬垫向下移动到所述第一多个硅散热片的上表面; 并使氧化物凹陷。

公开(公告)号：US20140252480A1

公开(公告)日：2014-09-11

申请号：US14283881

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Werner Juengling

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/7853

Abstract: A device includes a plurality of trenches and fins defined in a substantially un-doped layer of semiconducting material, a gate insulation layer positioned on the fins and on the bottom of the trenches, a gate electrode and a device isolation structure. One method disclosed herein involves identifying a top width of each of a plurality of fins and a depth of a plurality of trenches to be formed in a substantially un-doped layer of semiconducting material, wherein, during operation, the device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to the device, performing at least one process operation to define the trenches and fins in the layer of semiconducting material, forming a gate insulation layer on the fins and on a bottom of the trenches and forming a gate electrode above the gate insulation layer.

Abstract translation: 一种器件包括限定在基本上未掺杂的半导体材料层中的多个沟槽和鳍片，位于鳍片上并位于沟槽底部的栅极绝缘层，栅电极和器件隔离结构。 本文公开的一种方法包括识别多个翅片中的每一个的顶部宽度以及要形成在基本上未掺杂的半导体材料层中的多个沟槽的深度，其中，在操作期间，该装置适于在 至少三个可区分的条件，取决于施加到器件的电压，执行至少一个工艺操作以限定半导体材料层中的沟槽和鳍片，在鳍片上和沟槽的底部上形成栅极绝缘层并形成 在栅极绝缘层上方的栅电极。

公开(公告)号：US08751985B1

公开(公告)日：2014-06-10

申请号：US13795198

申请日：2013-03-12

Applicant: Globalfoundries Inc.

Inventor： Sandeep Puri ,  Bipul C. Paul ,  Werner Juengling ,  Anurag Mittal

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Hierarchical layout versus schematic comparison with extraneous device elimination is provided. This includes obtaining a hierarchical layout netlist for a circuit design, the hierarchical layout netlist grouping arrayed devices of the circuit design into blocks repeated at a top level of a hierarchy of the hierarchical layout netlist. A modified hierarchical layout netlist defining active devices and connections thereof to top level pads of the circuit design is generated, in which extraneous devices are selectively removed from the obtained hierarchical layout netlist. The modified hierarchical layout netlist is verified against an input schematic netlist defining active devices of the circuit design and connections thereof to pads of the circuit design.

Abstract translation: 提供了层次布局与与外部设备消除的原理图比较。 这包括获得用于电路设计的分层布局网表，分层布局网表将电路设计的阵列设备分组成在分级布局网表的层次结构的顶层重复的块。 产生了将有源器件及其连接定义为电路设计的顶级焊盘的修改的分层布局网表，其中从获得的分层布局网表中选择性地移除了外来设备。 修改的分层布局网表针对定义电路设计的有源器件的输入原理图网表及其与电路设计的焊盘的连接来验证。

公开(公告)号：US08946050B2

公开(公告)日：2015-02-03

申请号：US13664214

申请日：2012-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Werner Juengling

IPC: H01L21/762

CPC classification number: H01L27/11 ,  H01L21/76229 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/0684 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method is provided for forming SRAM cells with low energy implants. Embodiments include forming deep trenches in a silicon substrate; forming a deep n-well or deep p-well around a bottom of each deep trench; filling the deep trenches with oxide; forming a first or second shallow trench between each pair of adjacent deep trenches; forming a first p-well or first n-well, respectively, above each deep n-well or p-well; forming a second n-well at a bottom of each first shallow trench; forming a p+ region above each second n-well on each side of each first shallow trench; filling the first shallow trenches with oxide; forming a second p-well at a bottom of each second shallow trench; filling the second shallow trenches with oxide; forming a p+ region above each second n-well on each side of each first shallow trench; and forming an n+ region above each second p-well.

Abstract translation: 提供了一种用于形成具有低能量注入的SRAM单元的方法。 实施例包括在硅衬底中形成深沟槽; 在每个深沟的底部周围形成一个深n井或深p井; 用氧化物填充深沟槽; 在每对相邻的深沟槽之间形成第一或第二浅沟槽; 分别在每个深n阱或p阱之上形成第一个p阱或第一个n阱; 在每个第一浅沟槽的底部形成第二个n阱; 在每个第一浅沟槽的每一侧上形成在每个第二n阱上方的p +区域; 用氧化物填充第一浅沟; 在每个第二浅沟槽的底部形成第二p阱; 用氧化物填充第二浅沟; 在每个第一浅沟槽的每一侧上形成在每个第二n阱上方的p +区域; 并在每个第二个p阱之上形成n +区。