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    Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
    71.
    发明授权
    Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device 有权
    用于在FinFET器件中形成栅极并在FinFET器件的沟道区域中减薄鳍片的方法

    公开(公告)号：US06764884B1

    公开(公告)日：2004-07-20

    申请号：US10405342

    申请日：2003-04-03

    Applicant: Bin Yu ,  Haihong Wang

    Inventor： Bin Yu ,  Haihong Wang

    IPC: H01L2184

    CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66818

    Abstract: A method of manufacturing a FinFET device includes forming a fin structure on an insulating layer. The fin structure includes a conductive fin. The method also includes forming source/drain regions and forming a dummy gate over the fin. The dummy gate may be removed and the width of the fin in the channel region may be reduced. The method further includes depositing a gate material to replace the removed dummy gate.

    Abstract translation: 制造FinFET器件的方法包括在绝缘层上形成翅片结构。 翅片结构包括导电翅片。 该方法还包括形成源极/漏极区域并在鳍片上形成虚拟栅极。 可以去除伪栅极，并且可以减小沟道区域中的鳍的宽度。 该方法还包括沉积栅极材料以取代去除的虚拟栅极。

    Damascene gate process with sacrificial oxide in semiconductor devices
    72.
    发明授权
    Damascene gate process with sacrificial oxide in semiconductor devices 有权
    在半导体器件中具有牺牲氧化物的镶嵌栅极工艺

    公开(公告)号：US06686231B1

    公开(公告)日：2004-02-03

    申请号：US10310777

    申请日：2002-12-06

    Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

    Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

    IPC: H01L2100

    CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

    Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and forming a gate structure over a channel portion of the fin structure. The method may also include forming a sacrificial oxide layer around the gate structure and removing the gate structure to define a gate recess within the sacrificial oxide layer. A metal gate may be formed in the gate recess, and the sacrificial oxide layer may be removed.

    Abstract translation: 制造半导体器件的方法可以包括在绝缘体上形成翅片结构，并在翅片结构的沟道部分上形成栅极结构。 该方法还可以包括在栅极结构周围形成牺牲氧化物层并去除栅极结构以在牺牲氧化物层内限定栅极凹槽。 可以在栅极凹部中形成金属栅极，并且可以去除牺牲氧化物层。

    Method of fabricating transistor having a single crystalline gate conductor
    73.
    发明授权
    Method of fabricating transistor having a single crystalline gate conductor 有权
    制造具有单晶栅极导体的晶体管的方法

    公开(公告)号：US06620671B1

    公开(公告)日：2003-09-16

    申请号：US09846813

    申请日：2001-05-01

    Applicant: Haihong Wang ,  Joong Jeon

    Inventor： Haihong Wang ,  Joong Jeon

    IPC: H01L218238

    CPC classification number: H01L21/28194 ,  H01L21/28035 ,  H01L29/4925 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656

    Abstract: A method of manufacturing an integrated circuit on a substrate provides a gate structure including single crystalline material. The method can provide a first amorphous or polycrystalline semiconductor layer above a top surface of the substrate and patterning the first amorphous semiconductor layer to form a first gate conductor. The process can also include utilizing solid phase epitaxy to form a single crystal layer above the first gate conductor and patterning the single crystal layer to form a second gate conductor including the single crystal layer.

    Abstract translation: 在衬底上制造集成电路的方法提供包括单晶材料的栅极结构。 该方法可以在衬底的顶表面上方提供第一非晶或多晶半导体层，并且对第一非晶半导体层进行构图以形成第一栅极导体。 该方法还可以包括利用固相外延在第一栅极导体上方形成单晶层，并构图单晶层以形成包括单晶层的第二栅极导体。

    Double and triple gate MOSFET devices and methods for making same
    74.
    发明授权
    Double and triple gate MOSFET devices and methods for making same 有权
    双栅极和三栅极MOSFET器件及其制造方法

    公开(公告)号：US08222680B2

    公开(公告)日：2012-07-17

    申请号：US10274961

    申请日：2002-10-22

    Applicant: Ming-Ren Lin ,  Judy Xilin An ,  Zoran Krivokapic ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

    Inventor： Ming-Ren Lin ,  Judy Xilin An ,  Zoran Krivokapic ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

    IPC: H01L29/72

    CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66818

    Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.

    Abstract translation: 双栅极金属氧化物半导体场效应晶体管（MOSFET）包括鳍状物，第一栅极和第二栅极。 第一个门形成在鳍的顶部。 第二个门围绕翅片和第一个门。 在另一实施方案中，三栅极MOSFET包括鳍片，第一栅极，第二栅极和第三栅极。 第一个门形成在鳍的顶部。 第二个门形成在翅片附近。 第三栅极形成在翅片附近并与第二栅极相对。

    Germanium MOSFET devices and methods for making same
    75.
    发明授权
    Germanium MOSFET devices and methods for making same 有权
    锗MOSFET器件及其制造方法

    公开(公告)号：US07781810B1

    公开(公告)日：2010-08-24

    申请号：US11538217

    申请日：2006-10-03

    Applicant: Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

    Inventor： Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

    IPC: H01L29/72

    CPC classification number: H01L29/7855 ,  H01L21/823821 ,  H01L29/42384 ,  H01L29/7843 ,  H01L29/78684

    Abstract: A device includes a fin, a first gate and a second gate. The first gate is formed adjacent a first side of the fin and includes a first layer of material having a first thickness and having an upper surface that is substantially co-planar with an upper surface of the fin. The second gate is formed adjacent a second side of the fin opposite the first side and includes a second layer of material having a second thickness and having an upper surface that is substantially co-planar with the upper surface of the fin, where the first thickness and the second thickness are substantially equal to a height of the fin.

    Abstract translation: 一种装置包括鳍片，第一栅极和第二栅极。 第一门形成在鳍片的第一侧附近，并且包括具有第一厚度并且具有与鳍片的上表面基本共面的上表面的第一材料层。 所述第二浇口邻近所述翅片的与所述第一侧相对的第二侧形成，并且包括具有第二厚度并具有与所述翅片的上表面基本共面的上表面的第二材料层，其中所述第一厚度 并且第二厚度基本上等于翅片的高度。

    Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication
    78.
    发明授权
    Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication 有权
    具有硅锗源/漏扩展的应变硅PMOS及其制造方法

    公开(公告)号：US07071065B1

    公开(公告)日：2006-07-04

    申请号：US10738716

    申请日：2003-12-17

    Applicant: Qi Xiang ,  Eric N. Paton ,  Haihong Wang

    Inventor： Qi Xiang ,  Eric N. Paton ,  Haihong Wang

    IPC: H01L21/336

    CPC classification number: H01L29/6656 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66916 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/802 ,  Y10S438/933

    Abstract: A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed on the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon germanium material. The shallow source and drain extensions do not extend into the strained silicon channel region. By forming the source and drain extensions in silicon germanium material rather than in silicon, source and drain extension distortions caused by the enhanced diffusion rate of boron in silicon are avoided.

    Abstract translation: 应变硅p型MOSFET利用形成在硅锗衬底上的应变硅沟道区。 在邻近于应变硅沟道区的端部的硅锗层上形成硅锗区，并且在硅锗材料中注入浅的源极和漏极延伸。 浅源极和漏极延伸部分不延伸到应变硅沟道区域。 通过在硅锗材料而不是在硅中形成源极和漏极延伸，避免了由硅中的增强的扩散速率引起的源极和漏极扩展失真。

    Tensile strained substrate
    79.
    发明申请
    Tensile strained substrate 有权
    拉伸应变基材

    公开(公告)号：US20060138479A1

    公开(公告)日：2006-06-29

    申请号：US11356606

    申请日：2006-02-17

    Applicant: Minh Ngo ,  Paul Besser ,  Ming Lin ,  Haihong Wang

    Inventor： Minh Ngo ,  Paul Besser ,  Ming Lin ,  Haihong Wang

    IPC: H01L29/76 ,  H01L23/58

    CPC classification number: H01L29/7843 ,  H01L29/1054 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/933 ,  H01L2924/00

    Abstract: An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

    Abstract translation: 示例性实施例涉及形成金属氧化物半导体场效应晶体管（MOSFET）的方法。 该方法包括提供一个衬底，该衬底具有形成在衬底上方的栅极，并且执行以下沉积步骤中的至少一个：在位于衬底上方的硅层上方的栅极和栅绝缘体周围沉积间隔层并形成间隔物; 在间隔物，栅极和硅层之上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积介电层。 沉积间隔层，沉积蚀刻停止层和沉积介电层中的至少一个包括增加硅层中的拉伸应变的高压缩沉积。

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