公开(公告)号：US20120281468A1

公开(公告)日：2012-11-08

申请号：US13320331

申请日：2011-08-10

申请人： Qingqing Liang ,  Xiaodong Tong ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Xiaodong Tong ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： G11C11/34

CPC分类号： G11C11/39 ,  G11C17/06 ,  G11C2213/72 ,  G11C2213/74 ,  H01L27/1027

摘要： The present disclosure provides a semiconductor device and a semiconductor memory device. The semiconductor device can be used as a memory cell, and may comprise a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence. A first data state may be stored in the semiconductor device by applying a forward bias, which is larger than a punch-through voltage VBO, between the first P-type semiconductor layer and the second N-type semiconductor layer. A second data state may be stored in the semiconductor device by applying a reverse bias, which is approaching to the reverse breakdown region of the semiconductor device, between the first P-type semiconductor layer and the second N-type semiconductor layer. In this way, the semiconductor device may be effectively used for data storage. The semiconductor memory device comprises an array of memory cells consisted of the semiconductor devices.

摘要翻译： 本公开提供了半导体器件和半导体存储器件。 半导体器件可以用作存储单元，并且可以包括依次布置的第一P型半导体层，第一N型半导体层，第二P型半导体层和第二N型半导体层。 第一数据状态可以通过在第一P型半导体层和第二N型半导体层之间施加大于穿通电压VBO的正向偏压来存储在半导体器件中。 第二数据状态可以通过在第一P型半导体层和第二N型半导体层之间施加正在接近半导体器件的反向击穿区域的反向偏压来存储在半导体器件中。 以这种方式，半导体器件可以有效地用于数据存储。 半导体存储器件包括由半导体器件组成的存储器单元的阵列。

公开(公告)号：US20120181509A1

公开(公告)日：2012-07-19

申请号：US13143932

申请日：2011-02-23

申请人： Qingqing Liang ,  Zhi Jin ,  Wenwu Wang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Zhi Jin ,  Wenwu Wang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L29/775 ,  H01L21/335

CPC分类号： H01L29/66045 ,  H01L29/1606 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78684

摘要： A graphene device structure and a method for manufacturing the same are provided. The graphene device structure comprises: a graphene layer; a gate region formed on the graphene layer; and a doped semiconductor region formed at one side of the gate region and connected with the graphene layer, wherein the doped semiconductor region is a drain region of the graphene device structure, and the graphene layer formed at one side of the gate region is a source region of the graphene device structure. The on/off ratio of the graphene device structure may be improved by the doped semiconductor region without increasing the band gaps of the graphene material, so that the applicability of the graphene material in CMOS devices may be enhanced without decreasing the carrier mobility of graphene materials and speed of the devices.

摘要翻译： 提供石墨烯器件结构及其制造方法。 石墨烯器件结构包括：石墨烯层; 形成在所述石墨烯层上的栅极区域; 以及形成在所述栅极区域的一侧并与所述石墨烯层连接的掺杂半导体区域，其中所述掺杂半导体区域是所述石墨烯器件结构的漏极区域，并且形成在所述栅极区域一侧的所述石墨烯层是源极 石墨烯器件结构的区域。 可以通过掺杂半导体区域改善石墨烯器件结构的开/关比，而不增加石墨烯材料的带隙，从而可以增强石墨烯材料在CMOS器件中的适用性，而不降低石墨烯材料的载流子迁移率 和设备的速度。

公开(公告)号：US20120168865A1

公开(公告)日：2012-07-05

申请号：US13144903

申请日：2011-02-25

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/78648 ,  H01L29/66545 ,  H01L29/66628

摘要： The invention relates to a transistor and a method for manufacturing the transistor. The transistor according to an embodiment of the invention may comprise: a substrate which comprises at least a back gate of the transistor, an insulating layer and a semiconductor layer stacked sequentially, wherein the back gate of the transistor is used for adjusting the threshold voltage of the transistor; a gate stack formed on the semiconductor layer, wherein the gate stack comprises a gate dielectric and a gate electrode formed on the gate dielectric; a spacer formed on sidewalls of the gate stack; and a source region and a drain region located on both sides of the gate stack, respectively, wherein the height of the gate stack is lower than the height of the spacer. The transistor enables the height of the gate stack to be reduced and therefore the performance of the transistor is improved.

摘要翻译： 本发明涉及晶体管及其制造方法。 根据本发明的实施例的晶体管可以包括：至少包括晶体管的背栅极，绝缘层和顺序层叠的半导体层的衬底，其中晶体管的背栅极用于调节晶体管的阈值电压 晶体管; 形成在所述半导体层上的栅极堆叠，其中所述栅极堆叠包括形成在所述栅极电介质上的栅极电介质和栅电极; 形成在栅叠层的侧壁上的间隔物; 以及分别位于栅极堆叠的两侧的源极区域和漏极区域，其中栅极叠层的高度低于间隔物的高度。 该晶体管能够降低栅极叠层的高度，从而提高晶体管的性能。

公开(公告)号：US20110227160A1

公开(公告)日：2011-09-22

申请号：US13063717

申请日：2010-09-25

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/28105 ,  H01L21/2815 ,  H01L21/823462 ,  H01L21/823468 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66659

摘要： A semiconductor device and a method of manufacturing the same are provided. The semiconductor device has a metal sidewall spacer on the sidewall of a gate electrode on the drain region side. The metal sidewall spacer is made of such metals as Ta, which has an oxygen scavenging effect and can effectively reduce EOT on the drain region side, and thus the ability to control the short channel is effectively increased. In addition, since EOT on the source region side is larger, the carrier mobility of the device will not be degraded. Moreover, such asymmetric device may have a better driving performance.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件在漏极区侧的栅电极的侧壁上具有金属侧壁间隔物。 金属侧壁间隔物由具有除氧效果的Ta等金属制成，能够有效地减少漏区侧面的EOT，有效地提高控制短路的能力。 此外，由于源区域侧的EOT较大，所以器件的载流子迁移率不会降低。 此外，这种不对称装置可能具有更好的驱动性能。

公开(公告)号：US20070007552A1

公开(公告)日：2007-01-11

申请号：US11160676

申请日：2005-07-05

申请人： Huilong Zhu ,  Brian Tessier ,  Huicai Zhong

发明人： Huilong Zhu ,  Brian Tessier ,  Huicai Zhong

IPC分类号： H01L21/8238 ,  H01L27/10

CPC分类号： H01L21/823807 ,  H01L21/823828 ,  H01L29/7843 ,  Y10S438/938

摘要： Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a latter deposited stressed layer. A mask position used to pattern the sacrificial layer is adjusted such that removal of the latter deposited stressed layer, using the sacrificial layer, leaves the dual stress layers in an aligned form. The methods result in dual stressed layers that do not overlap or underlap, thus avoiding processing problems created by those issues. A semiconductor device including the aligned dual stressed layers is also disclosed.

摘要翻译： 公开了用于形成用于增强NFET和PFET的性能的自对准双应力层的方法。 在一个实施例中，牺牲层用于去除后一沉积的应力层。 调整用于图案化牺牲层的掩模位置，使得使用牺牲层去除后者沉积的应力层以对准的形式离开双应力层。 这种方法导致双重应力层不重叠或不重叠，从而避免了由这些问题产生的处理问题。 还公开了包括对准的双重应力层的半导体器件。

公开(公告)号：US08779514B2

公开(公告)日：2014-07-15

申请号：US13144903

申请日：2011-02-25

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/78648 ,  H01L29/66545 ,  H01L29/66628

摘要： The invention relates to a transistor and a method for manufacturing the transistor. The transistor according to an embodiment of the invention may comprise: a substrate which comprises at least a back gate of the transistor, an insulating layer and a semiconductor layer stacked sequentially, wherein the back gate of the transistor is used for adjusting the threshold voltage of the transistor; a gate stack formed on the semiconductor layer, wherein the gate stack comprises a gate dielectric and a gate electrode formed on the gate dielectric; a spacer formed on sidewalls of the gate stack; and a source region and a drain region located on both sides of the gate stack, respectively, wherein the height of the gate stack is lower than the height of the spacer. The transistor enables the height of the gate stack to be reduced and therefore the performance of the transistor is improved.

摘要翻译： 本发明涉及晶体管及其制造方法。 根据本发明的实施例的晶体管可以包括：至少包括晶体管的背栅极，绝缘层和顺序层叠的半导体层的衬底，其中晶体管的背栅极用于调节晶体管的阈值电压 晶体管; 形成在所述半导体层上的栅极堆叠，其中所述栅极堆叠包括形成在所述栅极电介质上的栅极电介质和栅电极; 形成在栅叠层的侧壁上的间隔物; 以及分别位于栅极堆叠的两侧的源极区域和漏极区域，其中栅极叠层的高度低于间隔物的高度。 该晶体管能够降低栅极叠层的高度，从而提高晶体管的性能。

公开(公告)号：US08592911B2

公开(公告)日：2013-11-26

申请号：US13063717

申请日：2010-09-25

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L29/78

CPC分类号： H01L29/4983 ,  H01L21/28105 ,  H01L21/2815 ,  H01L21/823462 ,  H01L21/823468 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66659

摘要： A semiconductor device and a method of manufacturing the same are provided. The semiconductor device has a metal sidewall spacer on the sidewall of a gate electrode on the drain region side. The metal sidewall spacer is made of such metals as Ta, which has an oxygen scavenging effect and can effectively reduce EOT on the drain region side, and thus the ability to control the short channel is effectively increased. In addition, since EOT on the source region side is larger, the carrier mobility of the device will not be degraded. Moreover, such asymmetric device may have a better driving performance.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件在漏极区侧的栅电极的侧壁上具有金属侧壁间隔物。 金属侧壁间隔物由具有除氧效果的Ta等金属制成，能够有效地减少漏区侧面的EOT，有效地提高控制短路的能力。 此外，由于源区域侧的EOT较大，所以器件的载流子迁移率不会降低。 此外，这种不对称装置可能具有更好的驱动性能。

公开(公告)号：US08557677B2

公开(公告)日：2013-10-15

申请号：US13120792

申请日：2011-02-17

申请人： Qingqing Liang ,  Huicai Zhong ,  Chao Zhao ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Chao Zhao ,  Huilong Zhu

IPC分类号： H01L21/30

CPC分类号： H01L25/50 ,  H01L21/6835 ,  H01L23/481 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stack-type semiconductor device includes a semiconductor substrate; and a plurality of wafer assemblies arranged in various levels on the semiconductor substrate, in which the wafer assembly in each level includes an active part and an interconnect part, and the active part and the interconnect part each have conductive through vias, wherein the conductive through vias in the active part are aligned with the conductive through vias in the interconnect part in a vertical direction, so that the active part in each level is electrically coupled with the active part in the previous level and/or the active part in the next level by the conductive through vias. Such a stack-type semiconductor device and the related methods can be applied in a process after the FEOL or in a semiconductor chip packaging process and provide a 3-dimensional semiconductor device of high integration and high reliability.

摘要翻译： 堆叠型半导体器件包括半导体衬底; 以及在所述半导体衬底上以各种级别布置的多个晶片组件，其中每个级中的所述晶片组件包括有源部分和互连部分，并且所述有源部分和所述互连部件各自具有导电通孔，其中所述导电通孔 有源部分中的通孔在垂直方向上与互连部分中的导电通孔对准，使得每个电平中的有源部分与先前电平中的有源部分和/或下一级的有源部分电耦合 通过导电通孔。 这种叠层型半导体器件及相关方法可以在FEOL之后的工艺中或半导体芯片封装工艺中应用，并提供高集成度和高​​可靠性的三维半导体器件。

公开(公告)号：US20130140624A1

公开(公告)日：2013-06-06

申请号：US13807010

申请日：2011-11-30

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L21/28008 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66666 ,  H01L29/78642

摘要： The invention discloses a semiconductor structure comprising: a substrate, a conductor layer, and a dielectric layer surrounding the conductor layer on the substrate; a first insulating layer covering both of the conductor layer and the dielectric layer; a gate conductor layer formed on the first insulating layer, and a dielectric layer surrounding the gate conductor layer; and a second insulating layer covering both of the gate conductor layer and the dielectric layer surrounding the gate conductor layer; wherein a through hole filled with a semiconductor material penetrates through the gate conductor layer perpendicularly, the bottom of the through hole stops on the conductor layer, and a first conductor plug serving as a drain/source electrode is provided on the top of the through hole; and a second conductor plug serving as a source/drain electrode electrically contacts the conductor layer, and a third conductor plug serving as a gate electrode electrically contacts the gate conductor layer.

摘要翻译： 本发明公开了一种半导体结构，包括：衬底，导体层和围绕衬底上的导体层的电介质层; 覆盖所述导体层和所述电介质层的第一绝缘层; 形成在第一绝缘层上的栅极导体层和围绕栅极导体层的电介质层; 以及覆盖所述栅极导体层和围绕所述栅极导体层的所述电介质层的第二绝缘层; 其中填充有半导体材料的通孔垂直地穿过栅极导体层，通孔的底部停在导体层上，并且用作漏极/源极的第一导体插塞设置在通孔的顶部 ; 和用作源/漏电极的第二导体插头与导体层电接触，并且用作栅电极的第三导体插头电接触栅极导体层。

公开(公告)号：US20130015526A1

公开(公告)日：2013-01-17

申请号：US13380806

申请日：2011-08-09

申请人： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

发明人： Qingqing Liang ,  Huilong Zhu ,  Huicai Zhong

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/7849 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203

摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention comprises: a substrate which comprises a base layer, an insulating layer on the base layer, and a semiconductor layer on the insulating layer; and a first transistor and a second transistor formed on the substrate, the first and second transistors being isolated from each other by a trench isolation structure formed in the substrate. Wherein at least a part of the base layer under at least one of the first and second transistors is strained, and the strained part of the base layer is adjacent to the insulating layer. The semiconductor device according to the invention increases the speed of the device and thus improves the performance of the device.

摘要翻译： 本发明涉及半导体器件及其制造方法。 根据本发明实施例的半导体器件包括：基底，其包括基底层，基底层上的绝缘层和绝缘层上的半导体层; 以及形成在所述衬底上的第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管通过形成在所述衬底中的沟槽隔离结构彼此隔离。 其中在第一和第二晶体管中的至少一个晶体管下方的基底层的至少一部分被应变，并且基底层的应变部分与绝缘层相邻。 根据本发明的半导体器件增加了器件的速度，从而提高了器件的性能。