公开(公告)号：US6054348A

公开(公告)日：2000-04-25

申请号：US79880

申请日：1998-05-15

申请人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Mong-Song Liang

发明人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Mong-Song Liang

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L29/66659

摘要： A process for creating a semiconductor memory device, featuring the formation of FOX regions, after the creation of a source region, has been developed. The process features a source region, self-aligned to a first set of stacked gate structures, with the subsequent FOX region placed perpendicular to the source region, between a second set of stacked gate structures.

摘要翻译： 已经开发了在创建源区域之后形成FOX区域的半导体存储器件的制造工艺。 该过程的特征在于源区域与第一组堆叠的栅极结构自对准，随后的FOX区域垂直于源区域放置在第二组堆叠栅极结构之间。

公开(公告)号：US5726070A

公开(公告)日：1998-03-10

申请号：US622692

申请日：1996-03-26

申请人： Gary Hong ,  Ching-Hsiang Hsu

发明人： Gary Hong ,  Ching-Hsiang Hsu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/788 ,  H01L21/8247

CPC分类号： H01L21/28185 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7882 ,  H01L21/28194

摘要： A process for forming an EEPROM having silicon rich tunnel oxide is disclosed. This oxide is used in the formation of flash EEPROMs and results in high tunneling current at low voltages. The oxide also results in EEPROMs having good endurance. A layer of silicon enriched with oxygen is formed between the substrate and the insulating layer separating the substrate from the floating gate.

摘要翻译： 公开了一种形成具有富硅隧道氧化物的EEPROM的工艺。 该氧化物用于形成快速EEPROM，并在低电压下产生高隧穿电流。 氧化物还导致具有良好耐久性的EEPROM。 在衬底和将衬底与浮动栅极分离的绝缘层之间形成富含氧的一层硅。

公开(公告)号：US5646431A

公开(公告)日：1997-07-08

申请号：US608385

申请日：1996-02-28

申请人： Ching-Hsiang Hsu ,  Da-Chi Kuo

发明人： Ching-Hsiang Hsu ,  Da-Chi Kuo

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66575 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/0619

摘要： A metal oxide semiconductor field effect transistor with a lightly doped silicon substrate includes an oppositely doped well and oppositely doped source region and oppositely doped drain region with respect to the lightly doped substrate, the improvement comprising at least one counter doped region formed along the surface of the oppositely doped well between the source and drain regions. The substrate comprises a P-substrate, the well comprises an N- well and the counter doped region is doped P; the counterdoped region comprises an island among a plurality of islands between the source region and the drain region. The counterdoped region comprises an island among a plurality of islands between the source region and the drain region.

摘要翻译： 具有轻掺杂硅衬底的金属氧化物半导体场效应晶体管包括相对于轻掺杂衬底的相对掺杂的阱和相对掺杂的源极区域和相对掺杂的漏极区域，改进包括至少一个沿着 在源极和漏极区之间的相反掺杂阱。 衬底包括P衬底，阱包括N阱，并且掺杂的掺杂区被掺杂P; 反向掺杂区域包括在源极区域和漏极区域之间的多个岛状区域中的岛状物。 反向掺杂区域包括在源极区域和漏极区域之间的多个岛状区域中的岛状物。

公开(公告)号：US07952934B2

公开(公告)日：2011-05-31

申请号：US12943937

申请日：2010-11-11

申请人： Riichiro Shirota ,  Ching-Hsiang Hsu ,  Cheng-Jye Liu

发明人： Riichiro Shirota ,  Ching-Hsiang Hsu ,  Cheng-Jye Liu

IPC分类号： G11C11/34

CPC分类号： G11C16/3418

摘要： A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the hole of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.

摘要翻译： 存储器结构包括位于相同位线并与第一存储器单元相邻的第一存储器单元和第二存储器单元。 每个存储单元包括衬底，源极，漏极，电荷存储器件和栅极。 用于对存储器结构进行编程的方法包括：分别向第一存储单元和第二存储单元的栅极提供第一栅极偏置电压和第二栅极偏置电压，提升第一存储单元的沟道电压的绝对值以产生 电子和空穴对，通过栅极引起的漏极泄漏或带对带通隧道在第二存储单元的漏极处，并且将所产生的电子和空穴对的空穴注入到第一存储器单元的电荷存储装置中以对 第一个存储单元

公开(公告)号：US20110051526A1

公开(公告)日：2011-03-03

申请号：US12943937

申请日：2010-11-11

申请人： Riichiro Shirota ,  Ching-Hsiang Hsu ,  Cheng-Jye Liu

发明人： Riichiro Shirota ,  Ching-Hsiang Hsu ,  Cheng-Jye Liu

IPC分类号： G11C16/12 ,  G11C17/08 ,  G11C11/40

CPC分类号： G11C16/3418

摘要： A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the hole of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.

摘要翻译： 存储器结构包括位于相同位线并与第一存储器单元相邻的第一存储器单元和第二存储器单元。 每个存储单元包括衬底，源极，漏极，电荷存储器件和栅极。 用于对存储器结构进行编程的方法包括：分别向第一存储单元和第二存储单元的栅极提供第一栅极偏置电压和第二栅极偏置电压，提升第一存储单元的沟道电压的绝对值以产生 电子和空穴对，通过栅极引起的漏极泄漏或带对带通隧道在第二存储单元的漏极处，并且将所产生的电子和空穴对的空穴注入到第一存储器单元的电荷存储装置中以对 第一个存储单元

公开(公告)号：US07846449B2

公开(公告)日：2010-12-07

申请号：US11778946

申请日：2007-07-17

申请人： Ching-Hsiang Hsu ,  Wei-Chih Su

发明人： Ching-Hsiang Hsu ,  Wei-Chih Su

IPC分类号： A61K39/00 ,  C07K14/00 ,  C07K17/00

CPC分类号： A61K39/35 ,  C07H21/04 ,  C07K14/43531 ,  Y10S530/868

摘要： The present invention provides a modified Dermatophagoides pteronyssinus allergen Der p 5 protein which has ability to inhibit IgE binding when exposed against to the antigen. A method for treating allergy comprising administrating a therapeutically effective dose of the modified D. pteronyssinus allergen Der p 5 protein to a subject suffering from allergy Der p 5 is also provided.

公开(公告)号：US20100289834A1

公开(公告)日：2010-11-18

申请号：US12775585

申请日：2010-05-07

申请人： Yung Ching LEE ,  Ching-Hsiang Hsu

发明人： Yung Ching LEE ,  Ching-Hsiang Hsu

IPC分类号： G09G5/10

CPC分类号： G09G3/3607 ,  G09G3/3413 ,  G09G5/39 ,  G09G2310/0235 ,  G09G2360/18

摘要： Field color sequential (FCS) control system applied for an FCS display device is provided. The FCS control system includes an input system, a memory and an output system. The input system, including a plurality of buffers respectively corresponding to different color channels, receives different color channel components of pixels in parallel such that components of a same color channel are stored in a same buffer. The memory, including a plurality of partitions respectively corresponding to different color channels, stores components of a same color channel to a same partition in association with triggering of rising and falling edges of a clock, respectively. The output system sequentially buffers and outputs color channel components of corresponding partitions.

摘要翻译： 提供了应用于FCS显示设备的场彩色顺序（FCS）控制系统。 FCS控制系统包括输入系统，存储器和输出系统。 包括分别对应于不同颜色通道的多个缓冲器的输入系统并行地接收像素的不同颜色通道分量，使得相同颜色通道的组件被存储在相同的缓冲器中。 包括分别对应于不同颜色通道的多个分区的存储器分别将时钟的上升沿和下降沿的触发相关联地存储到相同分区中的相同颜色通道的分量。 输出系统顺序地缓冲并输出相应分区的色彩通道分量。

公开(公告)号：US20100259552A1

公开(公告)日：2010-10-14

申请号：US12757660

申请日：2010-04-09

申请人： Ching-Hsiang Hsu

发明人： Ching-Hsiang Hsu

IPC分类号： G09G5/02

CPC分类号： G09G3/3611 ,  G09G3/3413 ,  G09G2310/0235 ,  G09G2320/0242 ,  G09G2320/0646

摘要： Field color sequential (FCS) imaging method and technology/apparatus based on FCS principle are provided. In an embodiment, while displaying a frame based on FCS principle, the invention includes: extracting at least a monochrome subfield value and at least a mixed subfield value from each color channel of each pixel of the frame, writing corresponding monochrome subfield value of each pixel in association with a single color channel, and writing corresponding mixed subfield value of each pixel in association with a mixed color which is mixed by at least two color channels.

摘要翻译： 提供了基于FCS原理的场彩色顺序（FCS）成像方法和技术/设备。 在一个实施例中，在基于FCS原理显示帧的同时，本发明包括：从帧的每个像素的每个颜色通道提取至少一个单色子字段值和至少一个混合子字段值，写入每个像素的相应单色子字段值 与单个颜色通道相关联，并且与通过至少两个颜色通道混合的混合颜色相关联地写入每个像素的相应混合子场值。

公开(公告)号：US20090168531A1

公开(公告)日：2009-07-02

申请号：US12144645

申请日：2008-06-24

申请人： Riichiro Shirota ,  Ching-Hsiang Hsu ,  Cheng-Jye Liu

发明人： Riichiro Shirota ,  Ching-Hsiang Hsu ,  Cheng-Jye Liu

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.

摘要翻译： 存储器结构包括位于相同位线并与第一存储器单元相邻的第一存储器单元和第二存储器单元。 每个存储单元包括衬底，源极，漏极，电荷存储器件和栅极。 一种用于对存储器结构进行编程的方法包括分别向第一存储单元和第二存储单元提供第一栅极偏置电压和第二栅极偏置电压，提高第一存储单元的沟道电压的绝对值以产生电子和空穴 通过栅极引起的漏极泄漏或带对带隧穿在第二存储单元的漏极处对，并将所产生的电子和空穴对的电子注入到第一存储单元的电荷存储装置中，以对第一存储单元 。

公开(公告)号：US20090010339A1

公开(公告)日：2009-01-08

申请号：US11773875

申请日：2007-07-05

申请人： Ching-Hsiang Hsu ,  Ling-Chih Lu ,  Shih-Chieh Lu

发明人： Ching-Hsiang Hsu ,  Ling-Chih Lu ,  Shih-Chieh Lu

IPC分类号： H04N7/32

CPC分类号： G09G3/3648 ,  G09G2320/0252 ,  G09G2320/0261 ,  G09G2320/0285 ,  G09G2340/16

摘要： Input image signals are spatially and temporally compensated. First, gray scales of a target pixel in a current frame and in a previous frame are compared to determine whether to spatially and temporally compensate the input image signals or not. Next, in accordance to weight parameters and gray scales of pixels adjacent to the target pixel, the target pixel of the current frame is spatially compensated. Further, based on the gray scale of the target pixel of the previous frame, the target pixel of the current frame after spatial compensation is temporally compensated.

摘要翻译： 输入图像信号在空间和时间上得到补偿。 首先，比较当前帧和先前帧中的目标像素的灰度级，以确定是否对输入图像信号进行空间和时间补偿。 接下来，根据与目标像素相邻的像素的权重参数和灰度级，对当前帧的目标像素进行空间补偿。 此外，基于前一帧的目标像素的灰度级，空间补偿后的当前帧的目标像素被时间上补偿。