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    Method for Producing a Pillar Structure in a Semiconductor Layer
    71.
    发明申请
    Method for Producing a Pillar Structure in a Semiconductor Layer 审中-公开

    公开(公告)号：US20170103889A1

    公开(公告)日：2017-04-13

    申请号：US15258838

    申请日：2016-09-07

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Vasile Paraschiv ,  Efrain Altamirano Sanchez ,  Zheng Tao

    IPC: H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/308

    Abstract: A method for producing a pillar structure in a semiconductor layer, the method including providing a structure including, on a main surface, a semiconductor layer. A patterned hard mask layer stack is provided on the semiconductor layer that includes a first layer in contact with the semiconductor layer and a second layer overlying and in contact with the first layer. The semiconductor layer is etched using the patterned hard mask layer stack as a mask. The etching includes subjecting the structure to a first plasma thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure, thereafter; and subjecting the structure to a second plasma thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure.

    INTEGRATED CIRCUIT CHIPS COMPRISING FORKSHEET DEVICES CONNECTED WITH BURIED POWER RAILS
    74.
    发明公开
    INTEGRATED CIRCUIT CHIPS COMPRISING FORKSHEET DEVICES CONNECTED WITH BURIED POWER RAILS 审中-公开

    公开(公告)号：US20240290660A1

    公开(公告)日：2024-08-29

    申请号：US18529121

    申请日：2023-12-05

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Gaspard Hiblot ,  Gioele Mirabelli

    IPC: H01L21/8234 ,  H01L27/088

    CPC classification number: H01L21/823475 ,  H01L21/823481 ,  H01L27/088

    Abstract: Integrated circuit chips and method for making integrated circuit chips are provided. The method includes providing a semiconductor substrate, forming a device layer including a forksheet device on the substrate and providing the substrate with a substrate part of a dielectric wall of the forksheet device, a first shallow trench isolation and a second shallow trench isolation. The method also includes contacting a source or drain contact and extending into the substrate between the first shallow trench isolation and the dielectric wall, then removing the substrate material so as to expose an end of the dielectric wall, the first surface, and the second surface, then obtaining a first spacer and a second spacer, so as to obtain a trench, wherein the end of the dielectric wall is exposed to the trench, then depositing an electrically insulating material in the trench so as to form an extension.

    Bit Cell with Isolating Wall
    78.
    发明公开
    Bit Cell with Isolating Wall 审中-公开

    公开(公告)号：US20230413505A1

    公开(公告)日：2023-12-21

    申请号：US18335320

    申请日：2023-06-15

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

    Inventor： Hsiao-Hsuan Liu ,  Shairfe Muhammad Salahuddin ,  Boon Teik Chan

    IPC: H10B10/00

    CPC classification number: H10B10/125

    Abstract: A bit cell for a Static Random-Access Memory (SRAM) is provided that includes a first and second pair of complementary transistors as well as a first pass-gate transistor and a second pass-gate transistor. A first inverter gate electrode forms a common gate electrode for the first pair of complementary transistors and a second inverter gate electrode forms a common gate electrode for the second pair of complementary transistors. Further, a first pass gate electrode forms a gate of the first pass-gate transistor and a second pass gate electrode forms a gate of the second pass-gate transistor. A first and a second dielectric wall are also provided, separating the first pass gate electrode from the first inverter gate electrode, and the second pass gate electrode from the second inverter gate electrode.

    Method for Forming a Stacked Transistor Device
    79.
    发明公开
    Method for Forming a Stacked Transistor Device 审中-公开

    公开(公告)号：US20230386928A1

    公开(公告)日：2023-11-30

    申请号：US18322213

    申请日：2023-05-23

    Applicant: IMEC VZW

    Inventor： Boon Teik Chan ,  Naoto Horiguchi ,  Julien Ryckaert

    IPC: H01L21/8234 ,  H01L29/66

    CPC classification number: H01L21/823456 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/66439

    Abstract: The present disclosure relates to a method for forming a stacked transistor device comprising a lower NSHFET structure and an upper FinFET structure including: forming a fin structure comprising: a lower device sub-stack comprising a number of lower channel nanosheets, a middle insulating layer, an upper device sub-stack comprising an upper channel layer, and a capping layer; forming a process layer embedding the fin structure; subsequent to forming the process layer, removing the capping layer from the fin structure to define a gap exposing the upper device sub-stack; forming spacer layers on opposite side surfaces of the gap to form a reduced-width gap; splitting the upper channel layer by etching back an upper surface thereof via the reduced-width gap to form two upper channel fins; subsequent to forming the upper channel fins, removing the spacer layers; and thereafter: forming a gate structure; and forming source and drain regions for the lower channel nanosheets and the upper channel fins.

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