公开(公告)号：US11699747B2

公开(公告)日：2023-07-11

申请号：US16365018

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Sarah Atanasov ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts ,  Stephanie A. Bojarski

IPC: H01L29/423 ,  G06N10/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/76 ,  B82Y10/00 ,  H01L29/775

CPC classification number: H01L29/775 ,  B82Y10/00 ,  G06N10/00 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66439 ,  H01L29/66977 ,  H01L29/7613 ,  H01L29/7831

Abstract: Disclosed herein are quantum dot devices with multiple layers of gate metal, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material above the quantum well stack, wherein the insulating material includes a trench; and a gate on the insulating material and extending into the trench, wherein the gate includes a first gate metal in the trench and a second gate metal above the first gate metal.

公开(公告)号：US20230197815A1

公开(公告)日：2023-06-22

申请号：US17556750

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Patrick Morrow ,  Gilbert Dewey ,  Willy Rachmady ,  Nicole K. Thomas ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/78618 ,  H01L27/088

Abstract: Techniques to form wrap-around contacts in a stacked transistor architecture. An example includes a first source or drain region and a second source or drain region spaced from and over the first source or drain region. A conductive contact is on a top surface of the second source or drain and extends down one or more side surfaces of the second source or drain region such that the conductive contact is laterally adjacent to a bottom surface of the second source or drain region. In some cases, the conductive contact is also on a top surface of the first source or drain region, and/or extends down a side surface of the first source or drain region. In some cases, a second conductive contact is on a bottom surface of the first source or drain region, and may extend up a side surface the first source or drain region.

公开(公告)号：US20230145229A1

公开(公告)日：2023-05-11

申请号：US17522342

申请日：2021-11-09

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ashish Agrawal ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Ehren Mannebach ,  Willy Rachmady ,  Marko Radosavljevic

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/78696 ,  H01L27/088

Abstract: Techniques are provided herein to form semiconductor devices having backside contacts. Sacrificial plugs are formed first within a substrate at particular locations to align with source and drain regions during a later stage of processing. Another wafer is subsequently bonded to the surface of the substrate and is thinned to effectively transfer different material layers to the top surface of the substrate. One of the transferred layers acts as a seed layer for the growth of additional semiconductor material used to form semiconductor devices. The source and drain regions of the semiconductor devices are sufficiently aligned over the previously formed sacrificial plugs. A backside portion of the substrate may be removed to expose the sacrificial plugs from the backside. Removal of the plugs and replacement of the recesses left behind with conductive material forms the conductive backside contacts to the source or drain regions.

公开(公告)号：US20230134379A1

公开(公告)日：2023-05-04

申请号：US17517925

申请日：2021-11-03

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Urusa Alaan ,  Susmita Ghose ,  Rambert Nahm ,  Natalie Briggs ,  Nicole K. Thomas ,  Willy Rachmady ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234

Abstract: Techniques are provided herein to form gate-all-around (GAA) semiconductor devices, such as those having a stacked transistor configuration. In one example case, two different semiconductor devices may both be GAA transistors each having any number of nanoribbons extending in the same (e.g., horizontal) direction where one device is located vertically above the other device. An internal spacer structure extends between the nanoribbons of both devices along the vertical direction, where the spacer structure includes one or more rib features between the two devices. A gate structure that includes one or more gate dielectric layers and one or more gate electrode layers may be formed around the nanoribbons of both devices, in some cases. In other cases, a split-gate configuration is used where upper and lower gate structures are separated by an isolation structure. Forksheet transistors and other GAA configurations may be formed using the techniques as well.

公开(公告)号：US11594599B2

公开(公告)日：2023-02-28

申请号：US16317023

申请日：2016-08-10

Applicant: Intel Corporation

Inventor： James S. Clarke ,  Robert L. Bristol ,  Ravi Pillarisetty ,  Jeanette M. Roberts ,  Hubert C. George ,  Nicole K. Thomas

IPC: H01L29/12 ,  H01L29/66 ,  H01L29/778 ,  H01L29/82 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/06 ,  H01L29/165 ,  H01L29/76

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a plurality of gates disposed above the quantum well stack, wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension.

公开(公告)号：US20230037957A1

公开(公告)日：2023-02-09

申请号：US17444678

申请日：2021-08-09

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Marko Radosavljevic

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and on the first gate structure. In addition, at least a portion of the second gate structure is on a central portion of the isolation structure and between first and second end portions of the isolation structure.

公开(公告)号：US11444188B2

公开(公告)日：2022-09-13

申请号：US16648402

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  Payam Amin ,  Zachary R. Yoscovits ,  Roman Caudillo ,  James S. Clarke

IPC: H01L29/778 ,  H01L29/12 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/165 ,  H01L29/66 ,  H01L29/76 ,  H01L29/82 ,  B82Y10/00 ,  B82Y40/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; an insulating material at least partially above the fin, wherein the insulating material includes a trench above the fin; and a gate metal on the insulating material and extending into the trench.

公开(公告)号：US20220147858A1

公开(公告)日：2022-05-12

申请号：US17583264

申请日：2022-01-25

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Hubert C. George ,  Jeanette M. Roberts ,  Nicole K. Thomas ,  James S. Clarke

IPC: G06N10/40 ,  H01L33/50 ,  H01L33/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base and a fin extending away from the base and including a quantum well layer. The device may further include a first gate disposed on a first side of the fin and a second gate disposed on a second side of the fin, different from the first side. Providing gates on different sides of a fin advantageously allows increasing the number of quantum dots which may be independently formed and manipulated in the fin. The quantum dots formed in such a device may be constrained in the x-direction by the one or more gates, in the y-direction by the fin, and in the z-direction by the quantum well layer, as discussed in detail herein. Methods for fabricating such devices are also disclosed.

公开(公告)号：US20210036110A1

公开(公告)日：2021-02-04

申请号：US16648442

申请日：2017-12-17

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Payam Amin ,  Hubert C. George ,  Jeanette M. Roberts ,  Roman Caudillo ,  David J. Michalak ,  Zachary R. Yoscovits ,  Lester Lampert

IPC: H01L29/12 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

公开(公告)号：US10910488B2

公开(公告)日：2021-02-02

申请号：US16019334

申请日：2018-06-26

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Lester Lampert ,  James S. Clarke ,  Ravi Pillarisetty ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts

IPC: H01L29/775 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/12 ,  H01L29/40 ,  H01L29/76 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/778 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin has a first side face and a second side face, and the fin includes a quantum well layer; and a gate above the fin, wherein the gate extends down along the first side face.