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公开(公告)号：US20150143201A1
公开(公告)日：2015-05-21
申请号：US14084043
申请日：2013-11-19
发明人： Paul W. Coteus , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Kenneth L. Wright
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1012 , G06F11/108 , G06F2211/109
摘要： According to one embodiment, a memory system includes a plurality of memory devices and a memory controller operatively coupled to the memory devices. The memory controller is configured to partition write data into a plurality of data blocks, where each data block is associated with one of the memory devices. The memory controller is further configured to generate an instance of a local error-correcting code (ECC) corresponding to each data block, and merge each data block with the corresponding instance of the local ECC to form an encoded data block for each memory device. Additionally, the memory controller is configured to write each encoded data block to the memory devices such that each memory device stores one of the data blocks with the corresponding instance of the local ECC. A global ECC and a local ECC of the global ECC can also be included in the memory system.
摘要翻译： 根据一个实施例，存储器系统包括多个存储器件和可操作地耦合到存储器件的存储器控制器。 存储器控制器被配置为将写入数据分割成多个数据块，其中每个数据块与存储器件之一相关联。 存储器控制器还被配置为生成对应于每个数据块的本地纠错码（ECC）的实例，并且将每个数据块与本地ECC的对应实例合并，以形成每个存储器设备的编码数据块。 另外，存储器控制器被配置为将每个编码的数据块写入存储器件，使得每个存储器件将数据块中的一个与本地ECC的对应实例一起存储。 全局ECC的全局ECC和本地ECC也可以包含在内存系统中。
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公开(公告)号：US08890316B2
公开(公告)日：2014-11-18
申请号：US14150600
申请日：2014-01-08
IPC分类号： H01L21/768 , H01L23/48 , H01L25/065 , H01L23/498
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/498 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L2224/0401 , H01L2224/05009 , H01L2224/05027 , H01L2224/13014 , H01L2224/13021 , H01L2224/13025 , H01L2224/131 , H01L2224/14051 , H01L2224/1411 , H01L2224/1613 , H01L2224/16146 , H01L2224/17106 , H01L2224/73204 , H01L2225/06513 , H01L2225/06541 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
摘要： A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled with a conducting material. A layer of glass is grown on both the top and bottom of the DRAM providing an insulator. A layer of metal is grown on each glass layer providing a conductor. The metal and glass layers are etched through to TSVs with a gap provided around the perimeter of via pads. A respective solder ball is formed on the TSVs to connect to another DRAM chip in the DRAM TSV stack. The metal layers are connected to at least one TSV by one respective solder ball and are connected to a voltage source and a dielectric is inserted between the metal layers in the DRAM TSV stack to complete the decoupling capacitor.
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73.发明授权公开(公告)号：US08797823B2
公开(公告)日：2014-08-05
申请号：US13658226
申请日：2012-10-23
CPC分类号： G06F17/5059 , G06F2217/84 , G11C7/1072 , G11C8/18
摘要： A method and circuit for implementing faster-cycle-time and lower-energy write operations for Synchronous Dynamic Random Access Memory (SDRAM), and a design structure on which the subject circuit resides are provided. A first RAS (row address strobe) to CAS (column address strobe) command delay (tRCD) is provided to the SDRAM for a read operation. A second delay tRCD is provided for a write operation that is substantially shorter than the first delay tRCD for the read operation.
摘要翻译： 用于实现用于同步动态随机存取存储器（SDRAM）的更快周期时间和较低能量写入操作的方法和电路，以及提供主题电路所在的设计结构。 向SDRAM（第一列地址选通）命令延迟（tRCD）的第一个RAS（行地址选通）提供给SDRAM用于读取操作。 提供第二延迟tRCD用于写操作，该写操作实质上比读操作的第一延迟tRCD短。
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公开(公告)号：US20220365685A1
公开(公告)日：2022-11-17
申请号：US17320269
申请日：2021-05-14
IPC分类号： G06F3/06
摘要： In an approach a request to write data to memory is received, wherein the memory includes: a first set of dynamic random-access memory (DRAM) accessible via a first memory channel, and a first set of storage class (SCM) memory accessible via a second memory channel. The data is written to the first set of DRAM via the first memory channel. The data is mirrored to the first set of SCM via the second memory channel.
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公开(公告)号：US11017875B2
公开(公告)日：2021-05-25
申请号：US16363110
申请日：2019-03-25
摘要： Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.
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公开(公告)号：US10971246B2
公开(公告)日：2021-04-06
申请号：US16387846
申请日：2019-04-18
IPC分类号： G11C29/00 , G06F11/10 , G06F12/1009 , G06F12/0871 , G06F3/06
摘要： Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.
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公开(公告)号：US20200226040A1
公开(公告)日：2020-07-16
申请号：US16828380
申请日：2020-03-24
摘要： A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.
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公开(公告)号：US10671497B2
公开(公告)日：2020-06-02
申请号：US15875136
申请日：2018-01-19
摘要： A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.
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公开(公告)号：US20200013449A1
公开(公告)日：2020-01-09
申请号：US16577644
申请日：2019-09-20
IPC分类号： G11C11/4074 , G11C5/14
摘要： A memory subsystem is disclosed comprising at least one memory module, the memory module having a substrate to which a plurality of memory chips is mounted and a voltage regulator, the voltage regulator receiving a power supply signal from a system power supply and outputting two or more power signals, each power signal providing a different, regulated voltage, which regulated voltages are each routed to each of the memory chips; and a redundant voltage regulator external to and not mounted on the memory module and configured to output two or more power signals, providing external different, regulated voltages which are the same voltages as the voltages output by the voltage regulator on the memory module, and supplying the two or more signals to the memory module.
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公开(公告)号：US20190317856A1
公开(公告)日：2019-10-17
申请号：US15953805
申请日：2018-04-16
发明人： James A. O'Connor, JR. , Barry M. Trager , Warren E. Maule , Marc A. Gollub , Brad W. Michael , Patrick J. Meaney
摘要： Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.
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