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    INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT
    71.
    发明申请
    INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT 有权
    集成电路和使用集成工艺步骤形成集成电路的深层隔离分离结构和深层电容电容器结构的方法

    公开(公告)号：US20110133310A1

    公开(公告)日：2011-06-09

    申请号：US12630091

    申请日：2009-12-03

    申请人： Brent A. Anderson ,  Andres Bryant ,  Herbert L. Ho ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  Herbert L. Ho ,  Edward J. Nowak

    IPC分类号： H01L29/92 ,  H01L21/8242

    CPC分类号： H01L21/76224 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/66181

    摘要： Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).

    摘要翻译： 公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。 形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。 在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。 因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。 在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

    INTEGRATED CIRCUIT DEVICE WITH SERIES-CONNECTED FIN-TYPE FIELD EFFECT TRANSISTORS AND INTEGRATED VOLTAGE EQUALIZATION AND METHOD OF FORMING THE DEVICE
    72.
    发明申请
    INTEGRATED CIRCUIT DEVICE WITH SERIES-CONNECTED FIN-TYPE FIELD EFFECT TRANSISTORS AND INTEGRATED VOLTAGE EQUALIZATION AND METHOD OF FORMING THE DEVICE 失效
    具有串联型FIN型场效应晶体管和集成电压均衡的集成电路装置及其形成方法

    公开(公告)号：US20110068414A1

    公开(公告)日：2011-03-24

    申请号：US12563194

    申请日：2009-09-21

    申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    IPC分类号： H01L27/088 ,  H01L21/8234

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： Disclosed is an integrated circuit device having stacked fin-type field effect transistors (FINFETs) with integrated voltage equalization and a method. A multi-layer fin includes a semiconductor layer, an insulator layer above the semiconductor layer and a high resistance conductor layer above the insulator layer. For each FINFET, a gate is positioned on the sidewalls and top surface of the fin and source/drain regions are within the semiconductor layer on both sides of the gate. Thus, the portion of the semiconductor layer between any two gates contains a source/drain region of one FINFET abutting a source/drain region of another. Conductive straps are positioned on opposing ends of the fin and also between adjacent gates in order to electrically connect the semiconductor layer to the conductor layer. Contacts electrically connect the conductive straps at the opposing ends of the fin to positive and negative supply voltages, respectively.

    摘要翻译： 公开了具有集成电压均衡的堆叠鳍式场效应晶体管（FINFET）的集成电路器件和方法。 多层翅片包括半导体层，半导体层上方的绝缘体层和绝缘体层上方的高电阻导体层。 对于每个FINFET，栅极位于鳍的侧壁和顶表面上，并且源/漏区在栅极两侧的半导体层内。 因此，任何两个栅极之间的半导体层的部分包含邻接另一栅极的源极/漏极区域的一个FINFET的源极/漏极区域。 导电带位于鳍的相对端并且还位于相邻栅之间，以将半导体层电连接到导体层。 触头将鳍片的相对端处的导电带分别电连接到正和负电源电压。

    Fin device with capacitor integrated under gate electrode
    73.
    发明授权
    Fin device with capacitor integrated under gate electrode 有权
    带电容器的Fin器件集成在栅电极下

    公开(公告)号：US07741184B2

    公开(公告)日：2010-06-22

    申请号：US11761438

    申请日：2007-06-12

    申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L27/1203 ,  H01L29/66795

    摘要： A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator covering the channel portion and the channel extensions, and a gate conductor on the gate insulator. The channel extensions increase capacitance of the channel portion of the fin.

    摘要翻译： 翅片型场效应晶体管（FinFET）具有鳍状物，其具有中心沟道部分，端部包括源极和漏极区域以及从鳍片的沟道部分的侧壁延伸的沟道延伸部。 该结构还包括覆盖沟道部分和沟道延伸部的栅极绝缘体以及栅极绝缘体上的栅极导体。 通道扩展增加了鳍片的通道部分的电容。

    Double-gate FETs (field effect transistors)
    74.
    发明授权
    Double-gate FETs (field effect transistors) 失效
    双栅极FET（场效应晶体管）

    公开(公告)号：US07718489B2

    公开(公告)日：2010-05-18

    申请号：US11436480

    申请日：2006-05-18

    申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

    摘要： A semiconductor structure and method for forming the same. The structure includes multiple fin regions disposed between first and second source/drain (S/D) regions. The structure further includes multiple front gates and back gates, each of which is sandwiched between two adjacent fin regions such that the front gates and back gates are alternating (i.e., one front gate then one back gate and then one front gate, and so on). The widths of the front gates are greater than the widths of the back gates. The capacitances of between the front gates and the S/D regions are smaller than the capacitances of between the back gates and the S/D regions. The distances between the front gates and the S/D regions are greater than the distances between the back gates and the S/D regions.

    摘要翻译： 一种半导体结构及其形成方法。 该结构包括设置在第一和第二源极/漏极（S / D）区域之间的多个鳍片区域。 该结构还包括多个前门和后门，每个前门和后门夹在两个相邻鳍片区域之间，使得前门和后门交替（即，一个前门，然后一个后门，然后一个前门，等等 ）。 前门的宽度大于后门的宽度。 前门和S / D区之间的电容小于后门和S / D区之间的电容。 前门和S / D区之间的距离大于后门和S / D区之间的距离。

    METHODS OF FABRICATING DUAL-DEPTH TRENCH ISOLATION REGIONS FOR A MEMORY CELL
    75.
    发明申请
    METHODS OF FABRICATING DUAL-DEPTH TRENCH ISOLATION REGIONS FOR A MEMORY CELL 审中-公开
    制备记忆细胞的双深度分离分离区的方法

    公开(公告)号：US20090269897A1

    公开(公告)日：2009-10-29

    申请号：US12111266

    申请日：2008-04-29

    申请人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Michael A. Guillorn ,  Ryoji Hasumi ,  Edward J. Nowak ,  Mickey H. Yu

    发明人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Michael A. Guillorn ,  Ryoji Hasumi ,  Edward J. Nowak ,  Mickey H. Yu

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823481 ,  H01L27/1104

    摘要： Methods for fabricating dual-depth trench isolation regions for a memory cell. First and second deep trench isolation regions are formed in the semiconductor layer that laterally bound a device region in a well of a first conductivity type in the semiconductor layer. First and second pluralities of doped regions of a second conductivity type are formed in the device region. A shallow trench isolation region is formed that extends laterally across the device region from the first deep trench isolation region to the second deep trench isolation region. The shallow trench isolation region is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends into the semiconductor layer to a depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions.

    摘要翻译： 用于制造用于存储单元的双深度沟槽隔离区域的方法。 在半导体层中形成第一和第二深沟槽隔离区域，该半导体层横向地限定半导体层中的第一导电类型的阱中的器件区域。 在器件区域中形成第二导电类型的第一和第二多个掺杂区域。 形成了浅沟槽隔离区域，其横跨穿过器件区域从第一深沟槽隔离区域延伸到第二深沟槽隔离区域。 浅沟槽隔离区设置在第一和第二多个掺杂区域之间的器件区域中。 浅沟槽隔离区域延伸到半导体层中的深度，使得阱在浅沟槽隔离区域之下是连续的。 栅极堆叠控制一对第一多个掺杂区域之间的载流子流动。

    RECESSED GATE CHANNEL WITH LOW Vt CORNER
    77.
    发明申请
    RECESSED GATE CHANNEL WITH LOW Vt CORNER 有权
    具有低Vt角的后门通道

    公开(公告)号：US20080268588A1

    公开(公告)日：2008-10-30

    申请号：US11741898

    申请日：2007-04-30

    申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    IPC分类号： H01L21/8238 ,  H01L27/01

    CPC分类号： H01L29/665 ,  H01L29/1083 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66621 ,  H01L29/78

    摘要： A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region. The recessed gate FET device suppresses short channel effects and exhibits improved threshold voltage (Vt) characteristics at corners of the trench bottom.

    摘要翻译： 凹陷栅极FET器件包括具有上部和下部的衬底，下部具有比上部更低的掺杂剂材料的浓度; 限定周围通道区域并且具有衬底的栅介质材料层的沟槽型栅电极，并且包括具有凹陷的顶表面的导电材料，以减少相对于在上基板表面处形成的源极和漏极扩散区域的重叠电容 侧电极。 在栅电极的任一侧和邻接栅电极处可选地形成卤素植入物，每个卤素注入物延伸到源极和漏极扩散到沟道区域之内。 此外，形成高掺杂的源极和漏极延伸区域，其提供从源极和漏极扩散区域到沟道区域的低电阻路径。 凹陷栅极FET器件抑制短沟道效应并且在沟槽底部的拐角处表现出改进的阈值电压（Vt）特性。

    Finfet/trigate stress-memorization method
    79.
    发明授权
    Finfet/trigate stress-memorization method 有权
    Finfet / Trigate应力记忆法

    公开(公告)号：US07341902B2

    公开(公告)日：2008-03-11

    申请号：US11379581

    申请日：2006-04-21

    申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

    IPC分类号： H01L21/336

    CPC分类号： H01L21/324 ,  H01L21/26586 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7851

    摘要： Disclosed are embodiments a technique for inducing strain into the polysilicon gate of a non-planar FET (e.g., a finFET or trigate FET) in order to impart a similar strain on the FET channel region, while simultaneously protecting the source/drain regions of the semiconductor fin. Specifically, a protective cap layer is formed above the source/drain regions of the fin in order to protect those regions during a subsequent amporphization ion implantation process. The fin is further protected, during this implantation process, because the ion beam is directed towards the gate in a plane that is parallel to the fin and tilted from the vertical axis. Thus, amorphization of the fin and damage to the fin are limited. Following the implantation process and the formation of a straining layer, a recrystallization anneal is performed so that the strain of the straining layer is ‘memorized’ in the polysilicon gate.

    摘要翻译： 公开了一种用于在非平面FET（例如，finFET或触发FET）的多晶硅栅极中诱导应变的技术，以便在FET沟道区上施加类似的应变，同时保护FET的源极/漏极区域 半导体鳍片 具体地，在翅片的源极/漏极区域之上形成保护盖层，以便在随后的悬空离子注入工艺期间保护这些区域。 在该植入过程期间，翅片被进一步保护，因为离子束在平行于翅片并从垂直轴倾斜的平面中朝向栅极。 因此，翅片的非晶化和鳍的损害是有限的。 在注入工艺和形成应变层之后，进行再结晶退火，使得应变层的应变“存储在多晶硅栅极中”。