公开(公告)号：US08324036B2

公开(公告)日：2012-12-04

申请号：US12614986

申请日：2009-11-09

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

IPC分类号： H01L21/84

CPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/66818

摘要： A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.

摘要翻译： 一种用于制造用于集成电路的特征的方法包括图案化心轴层以包括在集成电路器件的表面上具有至少一个宽度的结构。 结构的暴露的侧壁反应以在侧壁中一体地形成新的化合物，使得新化合物以受控的量延伸到暴露的侧壁中以形成柱。 使用柱作为蚀刻掩模蚀刻柱下方的一个或多个层，以形成用于集成电路器件的特征。

公开(公告)号：US08318574B2

公开(公告)日：2012-11-27

申请号：US12847208

申请日：2010-07-30

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L21/20

CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/10867

摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having of a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, where the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion of the top silicon layer, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.

摘要翻译： 在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在所述顶部硅层上的器件，其中所述器件耦合到所述顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背侧带的至少第一部分位于顶部硅层的掺杂部分的下面，背面带在背面的第一端耦合到顶部硅层的掺杂部分 带子和背部带子的第二端处的电容器; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。

公开(公告)号：US20120286350A1

公开(公告)日：2012-11-15

申请号：US13558518

申请日：2012-07-26

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

IPC分类号： H01L29/78

CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78

摘要： An FET device characterized as being an asymmetrical tunnel FET (TFET) is disclosed. The TFET includes a gate-stack, a channel region underneath the gate-stack, a first and a second junction adjoining the gate-stack and being capable for electrical continuity with the channel. The first junction and the second junction are of different conductivity types. The TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side.

摘要翻译： 公开了一种以不对称隧道FET（TFET）为特征的FET器件。 TFET包括栅极堆叠，栅极堆叠下方的沟道区域，邻接栅极叠层的第一和第二结，并且能够与沟道电连接。 第一接头和第二接头具有不同的导电类型。 TFET还包括间隔物结构，使得栅极叠层的一侧上的间隔物形成比另一侧更薄。

公开(公告)号：US20120261757A1

公开(公告)日：2012-10-18

申请号：US13531053

申请日：2012-06-22

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L29/78 ,  H01L27/092

CPC分类号： H01L29/66477 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618

摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.

摘要翻译： 一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一 在图案化的栅极结构下方的半导体衬底的沟道区上。

公开(公告)号：US20120256261A1

公开(公告)日：2012-10-11

申请号：US13083879

申请日：2011-04-11

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Tenko Yamashita ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Tenko Yamashita ,  Ying Zhang

IPC分类号： H01L29/772 ,  H01L21/31

CPC分类号： H01L21/28123 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203

摘要： A semiconductor device including a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.

摘要翻译： 一种半导体器件，包括具有至少一个氮化物材料衬里隔离腔的衬底; 以及含有铪的电介质填充物，其至少部分地包含在并且至少部分地覆盖所述至少一个氮化物衬里隔离腔的至少一部分。

公开(公告)号：US08263446B2

公开(公告)日：2012-09-11

申请号：US12881152

申请日：2010-09-13

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L21/00

CPC分类号： H01L29/66795 ,  H01L21/2633 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/517 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856

摘要： Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold-modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.

摘要翻译： 公开了非对称FET器件，以及在翅片结构上制造这种非对称器件的方法。 该制造方法包括在散热片上布置高k电介质层，随后是阈值修饰层，以倾斜角执行离子轰击，该倾斜角度在翅片的侧面之一上除去阈值修饰层。 完成的FET器件将是不对称的，因为阈值修饰层仅存在于翅片一侧的两个器件之一中。 在替代实施例中，引入另外的不对称性，再次使用倾斜离子注入，导致用于翅片每侧上的两个FinFET器件的不同的栅极 - 导体材料。

公开(公告)号：US08215074B2

公开(公告)日：2012-07-10

申请号：US12026123

申请日：2008-02-05

申请人： Charles T. Black ,  Timothy J. Dalton ,  Bruce B. Doris ,  Carl Radens

发明人： Charles T. Black ,  Timothy J. Dalton ,  Bruce B. Doris ,  Carl Radens

IPC分类号： E04B2/00

CPC分类号： H01L21/0338 ,  B81B2203/0369 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  H01L21/0337 ,  H01L51/0017 ,  Y10S977/882 ,  Y10S977/887 ,  Y10S977/888 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24612 ,  Y10T428/24736 ,  Y10T428/24802

摘要： In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.

摘要翻译： 在一个实施例中，包括大的六边形瓦片被分成三组，每组包含彼此分离的所有六边形瓦片的1/3。 每个组中的六边形瓦片的开口形成在模板层中，并且在每个开口内施加并组合一组自组装嵌段共聚物。 该过程重复三次以包含所有三组，导致在大面积上延伸的自对准图案。 在另一个实施例中，大面积被分成两个不重叠和互补组的矩形瓦片。 每个矩形区域的宽度小于自组装嵌段共聚物的顺序范围。 在每组中以顺序的方式形成自组装的自对准线和空间结构，使得在超过有序范围的大面积上形成线和空间图案。

公开(公告)号：US20120132966A1

公开(公告)日：2012-05-31

申请号：US11872291

申请日：2007-10-15

申请人： Bruce B. Doris ,  Carl J. Radens ,  Anthony K. Stamper ,  Jay W. Strane

发明人： Bruce B. Doris ,  Carl J. Radens ,  Anthony K. Stamper ,  Jay W. Strane

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/28518 ,  B81B2207/07 ,  B81C1/00095 ,  B81C2201/0149 ,  H01L21/3086 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.

摘要翻译： 自组装聚合物技术用于在存在于半导体结构的导电接触区域中的材料内形成至少一个有序的纳米尺度图案。 具有有序纳米尺寸图案的材料是场效应晶体管的互连结构或半导体源和漏极扩散区的导电材料。 在接触区域内有序的纳米尺寸图案材料的存在增加了用于随后的接触形成的总面积（即界面面积），这又降低了结构的接触电阻。 接触电阻的降低又改善了通过结构的电流的流动。 除了上述之外，本发明的方法和结构不影响结构的结电容，因为结面积保持不变。

公开(公告)号：US20120129357A1

公开(公告)日：2012-05-24

申请号：US12017598

申请日：2008-01-22

申请人： Timothy J. Dalton ,  Bruce B. Doris ,  Ho-Cheol Kim ,  Carl Radens

发明人： Timothy J. Dalton ,  Bruce B. Doris ,  Ho-Cheol Kim ,  Carl Radens

IPC分类号： H01L21/31 ,  B82Y40/00

CPC分类号： H01L21/0337 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/0338 ,  Y10T428/24612

摘要： A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.

摘要翻译： 具有亚光刻宽度和亚光刻距离并沿着第一方向延伸的第一纳米级自对准自组装嵌套线结构由第一层内的第一自组装嵌段共聚物形成。 第一层填充有填充材料，并且第二层沉积在包含第一纳米级嵌套线结构的第一层之上。 具有亚光刻宽度和亚光刻距离并沿第二方向运行的第二纳米级自对准自组装嵌套线结构由第二层内的第二自组装嵌段共聚物形成。 第一纳米级嵌套线结构和第二纳米级嵌套线结构的复合图案被转移到第一层下面的底层中以形成在两个方向上包含周期性的结构阵列。

公开(公告)号：US20120112279A1

公开(公告)日：2012-05-10

申请号：US12941042

申请日：2010-11-06

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong ,  Ying Zhang

IPC分类号： H01L29/772 ,  H01L29/45 ,  H01L21/28

CPC分类号： H01L29/41733 ,  H01L21/28518 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for contacting an FET device is disclosed. The method includes vertically recessing the device isolation, which exposes a sidewall surface on both the source and the drain. Next, silicidation is performed, resulting in a silicide layer covering both the top surface and the sidewall surface of the source and the drain. Next, metallic contacts are applied in such manner that they engage the silicide layer on both its top and on its sidewall surface. A device characterized as being an FET device structure with enlarged contact areas is also disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide on its top surface and on its sidewall surface.

摘要翻译： 公开了一种接触FET器件的方法。 该方法包括垂直凹陷器件隔离，其暴露源极和漏极两侧的侧壁表面。 接下来，进行硅化，得到覆盖源极和漏极的顶表面和侧壁表面的硅化物层。 接下来，以这样的方式施加金属触点，使得它们在其顶部和侧壁表面上接合硅化物层。 还公开了一种特征在于具有扩大的接触面积的FET器件结构的器件。 该装置具有垂直凹入的隔离，从而在源极和漏极两者上具有暴露的侧壁表面。 硅化物层覆盖源极和漏极的顶表面和侧壁表面。 与设备的金属接触件在其顶表面和其侧壁表面上接合硅化物。