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    EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT WITH ON-CHIP RESISTORS AND METHOD OF FORMING THE SAME
    71.
    发明申请
    EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT WITH ON-CHIP RESISTORS AND METHOD OF FORMING THE SAME 有权
    具有片上电阻的超薄半导体绝缘体（ETSOI）集成电路及其形成方法

    公开(公告)号：US20120187493A1

    公开(公告)日：2012-07-26

    申请号：US13433401

    申请日：2012-03-29

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    IPC分类号： H01L27/06 ,  H01L29/16

    CPC分类号： H01L27/1214 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/13

    摘要： An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.

    摘要翻译： 提供了一种电气装置，其在一个实施例中包括具有厚度小于10nm的半导体层的绝缘体上半导体（SOI）基板。 在半导体层的第一表面上存在具有第一导电性的单晶半导体材料的升高的源极区域和升高的漏极区域的半导体器件。 由第一导电性的单晶半导体材料构成的电阻器存在于半导体层的第二表面上。 还提供了形成上述电气装置的方法。

    METHOD AND STRUCTURE FOR FORMING HIGH-PERFOMANCE FETs WITH EMBEDDED STRESSORS
    73.
    发明申请
    METHOD AND STRUCTURE FOR FORMING HIGH-PERFOMANCE FETs WITH EMBEDDED STRESSORS 有权
    用嵌入式压力器形成高性能FET的方法和结构

    公开(公告)号：US20110068396A1

    公开(公告)日：2011-03-24

    申请号：US12566004

    申请日：2009-09-24

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/2257 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    摘要： A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a first epitaxy semiconductor material that induces a strain upon a channel of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.

    摘要翻译： 提供了高性能半导体结构和制造这种结构的方法。 半导体结构包括位于半导体衬底的上表面上的至少一个栅堆叠，例如FET。 该结构还包括在至少一个栅极堆叠的沟道上引起应变的第一外延半导体材料。 第一外延半导体材料位于至少一个栅极堆叠的基准面上，基本上位于衬底中的存在于至少一个栅极堆叠的相对侧上的一对凹陷区域内。 扩散扩展区域位于每个凹陷区域中的所述第一外延半导体材料的上表面内。 该结构还包括位于扩散扩展区的上表面上的第二外延半导体材料。 第二外延半导体材料具有比第一外延半导体材料更高的掺杂剂浓度。

    Extremely thin semiconductor-on-insulator (ETSOI) integrated circuit with on-chip resistors and method of forming the same
    74.
    发明授权
    Extremely thin semiconductor-on-insulator (ETSOI) integrated circuit with on-chip resistors and method of forming the same 有权
    具有片上电阻的非常薄的绝缘体上半导体（ETSOI）集成电路及其形成方法

    公开(公告)号：US08343819B2

    公开(公告)日：2013-01-01

    申请号：US12687273

    申请日：2010-01-14

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    IPC分类号： H01L21/00

    CPC分类号： H01L27/1214 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/13

    摘要： An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.

    摘要翻译： 提供了一种电气装置，其在一个实施例中包括具有厚度小于10nm的半导体层的绝缘体上半导体（SOI）基板。 在半导体层的第一表面上存在具有第一导电性的单晶半导体材料的升高的源极区域和升高的漏极区域的半导体器件。 由第一导电性的单晶半导体材料构成的电阻器存在于半导体层的第二表面上。 还提供了形成上述电气装置的方法。

    Tunnel field effect transistor
    75.
    发明授权
    Tunnel field effect transistor 有权
    隧道场效应晶体管

    公开(公告)号：US08318568B2

    公开(公告)日：2012-11-27

    申请号：US12760287

    申请日：2010-04-14

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

    IPC分类号： H01L21/336

    CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78

    摘要： A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack.

    摘要翻译： 公开了一种用于制造FET器件的方法，其特征在于是隧道FET（TFET）器件。 该方法包括处理栅极堆叠，以及处理第一导电类型的邻接的源极和漏极结。 形成覆盖栅极堆叠和结的硬掩模。 执行由硬掩模的第一部分接收的倾斜角度离子注入，并且由于栅极堆叠的阴影而不被硬掩模的第二部分接收。 去除硬掩模的注入部分，并露出其中一个接头。 该结被蚀刻掉，并且通常原位掺杂到第二导电类型的新结，外延生长到其位置。 还公开了一种特征为不对称TFET的器件。 TFET的源极和漏极结具有不同的导电类型，并且TFET还包括间隔物结构，使得栅极堆叠的一侧上的间隔物形成比栅极堆叠的另一侧更薄。

    Replacement Gate ETSOI with Sharp Junction
    79.
    发明申请
    Replacement Gate ETSOI with Sharp Junction 审中-公开
    更换门ETSOI与夏普结

    公开(公告)号：US20130032876A1

    公开(公告)日：2013-02-07

    申请号：US13195153

    申请日：2011-08-01

    申请人： Kangguo CHENG ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

    发明人： Kangguo CHENG ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

    IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795

    摘要： A transistor structure includes a channel disposed between a source and a drain; a gate conductor disposed over the channel and between the source and the drain; and a gate dielectric layer disposed between the gate conductor and the source, the drain and the channel. In the transistor structure a lower portion of the source and a lower portion of the drain that are adjacent to the channel are disposed beneath and in contact with the gate dielectric layer to define a sharply defined source-drain extension region. Also disclosed is a replacement gate method to fabricate the transistor structure.

    摘要翻译： 晶体管结构包括设置在源极和漏极之间的沟道; 设置在所述通道上并且在所述源极和所述漏极之间的栅极导体; 以及设置在栅极导体和源极之间的栅介质层，漏极和沟道。 在晶体管结构中，源极的下部和与沟道相邻的漏极的下部设置在栅极介电层的下方并与栅极介电层接触以限定明确限定的源 - 漏扩展区。 还公开了制造晶体管结构的替代栅极方法。

    Replacement gate ETSOI with sharp junction
    80.
    发明授权
    Replacement gate ETSOI with sharp junction 有权
    替换门ETSOI与尖端连接

    公开(公告)号：US08673708B2

    公开(公告)日：2014-03-18

    申请号：US13611044

    申请日：2012-09-12

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

    IPC分类号： H01L21/338

    CPC分类号： H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795

    摘要： A method includes providing a silicon-on-insulator wafer (e.g., an ETSOI wafer); forming a sacrificial gate structure that overlies a sacrificial insulator layer; forming raised source/drains adjacent to the sacrificial gate structure; depositing a layer that covers the raised source/drains and that surrounds the sacrificial gate structure; and removing the sacrificial gate structure leaving an opening that extends to the sacrificial insulator layer. The method further includes widening the opening so as to expose some of the raised source/drains, removing the sacrificial insulator layer and forming a spacer layer on sidewalls of the opening, the spacer layer covering only an upper portion of the exposed raised source/drains, and depositing a layer of gate dielectric material within the opening. A gate conductor is deposited within the opening.

    摘要翻译： 一种方法包括提供绝缘体上硅晶片（例如，ETSOI晶片）; 形成覆盖牺牲绝缘体层的牺牲栅极结构; 形成与牺牲栅极结构相邻的凸起的源极/漏极; 沉积覆盖升高的源极/漏极并围绕牺牲栅极结构的层; 以及去除牺牲栅极结构，留下延伸到牺牲绝缘体层的开口。 该方法还包括加宽开口以暴露一些升高的源极/漏极，去除牺牲绝缘体层并在开口的侧壁上形成间隔层，间隔层仅覆盖暴露的升高的源极/漏极的上部 ，并且在开口内沉积一层栅介质材料。 栅极导体沉积在开口内。