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128 条记录 (耗时 0.031 秒)

    Memory device including 3-dimensionally arranged memory cell transistors and methods of operating the same
    73.
    发明授权
    Memory device including 3-dimensionally arranged memory cell transistors and methods of operating the same 有权
    包括三维布置的存储单元晶体管的存储器件及其操作方法

    公开(公告)号：US07701771B2

    公开(公告)日：2010-04-20

    申请号：US11882769

    申请日：2007-08-06

    申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Hoo-Sung Cho

    发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Hoo-Sung Cho

    IPC分类号： G11C11/03

    CPC分类号： H01L27/115 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551

    摘要： A memory device may include L semiconductor layers, a gate structure on each of the semiconductor layers, N bitlines, and/or a common source line on each of the semiconductor layers. The L semiconductor layers may be stacked, and/or L may be an integer greater than 1. The N bitlines may be on the gate structures and crossing over the gate structures, and/or N may be an integer greater than 1. Each of the common source lines may be connected to each other such that the common source lines have equipotentiality with each other.

    摘要翻译： 存储器件可以包括L个半导体层，每个半导体层上的栅极结构，N个位线和/或每个半导体层上的公共源极线。 L个半导体层可以被堆叠，和/或L可以是大于1的整数.N个位线可以在栅极结构上并且跨过栅极结构，和/或N可以是大于1的整数。 公共源极线可以彼此连接，使得公共源极线彼此具有等电位。

    Methods of restoring data in flash memory devices and related flash memory device memory systems
    74.
    发明授权
    Methods of restoring data in flash memory devices and related flash memory device memory systems 有权
    在闪存设备和相关闪存设备存储器系统中恢复数据的方法

    公开(公告)号：US07542350B2

    公开(公告)日：2009-06-02

    申请号：US11616411

    申请日：2006-12-27

    申请人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

    发明人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

    IPC分类号： G11C16/04

    CPC分类号： G11C16/349 ,  G11C16/3495

    摘要： Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit number and a distribution read voltage, the data bit number indicating an erase state among the page data respectively read from the flash memory device and the distribution read voltage corresponding to the read page data; detecting distribution read voltages corresponding to data bit numbers each indicating maximum points of possible cell states of a memory cell, based on the distribution table; and defining new read voltages based on the detected distribution read voltages.

    摘要翻译： 包括闪速存储器装置和用于控制闪速存储器件的存储器控​​制器的存储器系统中设置读取电压的方法包括顺序地改变分配读取电压以从闪速存储器装置读取页面数据; 构成具有数据位数和分布读电压的分布表，分别表示从闪存器件分别读取的页数据中的擦除状态的数据位数和与读页数据相对应的分布读电压; 基于分布表，检测对应于每个表示存储器单元的可能单元状态的最大点的数据位数的分布读取电压; 以及基于检测到的分布读取电压来定义新的读取电压。

    Flash memory device capable of preventing coupling effect and program method thereof
    75.
    发明授权
    Flash memory device capable of preventing coupling effect and program method thereof 失效
    能够防止耦合效应的闪存装置及其编程方法

    公开(公告)号：US07535761B2

    公开(公告)日：2009-05-19

    申请号：US11637415

    申请日：2006-12-12

    申请人： Ki-Tae Park ,  Yeong-Taek Lee ,  Ki-Nam Kim

    发明人： Ki-Tae Park ,  Yeong-Taek Lee ,  Ki-Nam Kim

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3418 ,  G11C16/3427

    摘要： The present invention provides a flash memory device that includes a word line; even page cells that are physically adjacent and connected to the word line; and odd page cells that are physically adjacent and connected to the word line, wherein at a program operation, page data is programmed in either one of the even page cells or the odd page cells.

    摘要翻译： 本发明提供了一种包括字线的闪存器件; 物理上相邻并连接到字线的偶数页单元格; 以及物理上相邻并连接到字线的奇数页单元，其中在编程操作中，页数据被编程在偶数页单元或奇数页单元中的任何一个中。

    Phase change memory device and method for forming the same
    78.
    发明申请
    Phase change memory device and method for forming the same 失效
    相变存储器件及其形成方法

    公开(公告)号：US20080173862A1

    公开(公告)日：2008-07-24

    申请号：US12008125

    申请日：2008-01-09

    申请人： Yoon-Jong Song ,  Se-Ho Lee ,  Ki-Nam Kim ,  Su-Youn Lee ,  Jae-Hyun Park

    发明人： Yoon-Jong Song ,  Se-Ho Lee ,  Ki-Nam Kim ,  Su-Youn Lee ,  Jae-Hyun Park

    IPC分类号： H01L45/00

    CPC分类号： H01L45/06 ,  G11C2213/52 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/1683 ,  Y10S438/90

    摘要： A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical shape, having its sidewalls conformally disposed on the lower inner walls of the opening. The filling insulation pattern fills an empty region surrounded by the sidewalls of the heating electrode. The phase change material pattern is disposed on the mold layer and downwardly extended to fill the empty part of the opening. The phase change material pattern contacts the top surfaces of the sidewalls of the heating electrode.

    摘要翻译： 相变存储器件包括设置在基板上的模具层，加热电极，填充绝缘图案和相变材料图案。 加热电极设置在使基板穿过模具层的开口中。 加热电极形成为大致圆筒形，其侧壁共形地设置在开口的下内壁上。 填充绝缘图案填充由加热电极的侧壁围绕的空白区域。 相变材料图案设置在模具层上并向下延伸以填充开口的空的部分。 相变材料图案接触加热电极的侧壁的顶表面。

    Flash Memory Devices that Utilize Age-Based Verify Voltages to Increase Data Reliability and Methods of Operating Same
    79.
    发明申请
    Flash Memory Devices that Utilize Age-Based Verify Voltages to Increase Data Reliability and Methods of Operating Same 有权
    使用基于年龄的验证电压以提高数据可靠性的闪存设备和操作方法相同

    公开(公告)号：US20080117688A1

    公开(公告)日：2008-05-22

    申请号：US11943887

    申请日：2007-11-21

    申请人： Ki-Tae Park ,  Yong-Seok Kim ,  Ki-Nam Kim ,  Yeong-Taek Lee

    发明人： Ki-Tae Park ,  Yong-Seok Kim ,  Ki-Nam Kim ,  Yeong-Taek Lee

    IPC分类号： G11C11/34

    CPC分类号： G11C16/344 ,  G11C16/3454

    摘要： Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles.

    摘要翻译： 公开了一种验证闪速存储器件的编程状态的方法，其包括：响应于存储器单元的编程/擦除循环的数量确定额外的验证电压的电平; 对初始验证电压低于附加验证电压的程序存储单元执行验证操作; 以及响应于所述编程/擦除周期的数量，选择性地对所述经过程序验证的存储器单元执行附加验证电压的附加验证操作。