公开(公告)号：US20050032321A1

公开(公告)日：2005-02-10

申请号：US10637351

申请日：2003-08-08

申请人： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos Diaz ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos Diaz ,  Fu-Liang Yang

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

摘要： A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.

摘要翻译： 一种提高集成电路中MOS器件的载流子迁移率的结构。 该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

公开(公告)号：US20050019998A1

公开(公告)日：2005-01-27

申请号：US10627849

申请日：2003-07-25

申请人： Chien-Chao Huang ,  Tone-Xuan Chung ,  Cheng-Chuan Huang ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Tone-Xuan Chung ,  Cheng-Chuan Huang ,  Fu-Liang Yang

IPC分类号： H01L29/49 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/6656 ,  H01L29/7842 ,  H01L29/7843

摘要： A semiconductor device and the method for making same is disclosed. The semiconductor device has a substrate and a gate region on top of the substrate. It further has a first and second gate sidewall liners situated on a first and second sides of the gate region respectively, the first and second sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate; and a first and second recessed spacers situated on top of the first and second sidewall liners respectively, wherein a height of the first and second spacers is lower than a height of the gate sidewall liner and wherein the width of the horizontal part of the sidewall liner is shorter than the width of the spacer.

摘要翻译： 公开了一种半导体器件及其制造方法。 半导体器件在衬底的顶部具有衬底和栅极区域。 其还具有分别位于栅极区域的第一和第二侧上的第一和第二栅极侧壁衬里，第一和第二侧壁衬里具有接触栅极区域的侧壁和与衬底接触的水平部分的垂直部分; 以及分别位于第一和第二侧壁衬套的顶部上的第一和第二凹槽，其中第一和第二间隔件的高度低于门侧壁衬套的高度，并且其中侧壁衬套的水平部分的宽度 比间隔件的宽度短。

公开(公告)号：US09905474B2

公开(公告)日：2018-02-27

申请号：US13210993

申请日：2011-08-16

申请人： Chun-Sheng Liang ,  Hung-Ming Chen ,  Chien-Chao Huang ,  Fu-Liang Yang

发明人： Chun-Sheng Liang ,  Hung-Ming Chen ,  Chien-Chao Huang ,  Fu-Liang Yang

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor. The NMOS device in the NMOS region includes a second gate stack on the semiconductor substrate; a second offset spacer on a sidewall of the second gate stack; a second raised source/drain extension region on the semiconductor substrate and adjoining the second offset spacer; and a deep source/drain region adjoining the second raised source/drain extension region, wherein the deep source/drain region is free from stressors formed in the semiconductor substrate.

公开(公告)号：US20160240372A9

公开(公告)日：2016-08-18

申请号：US11714416

申请日：2007-03-06

申请人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

发明人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

IPC分类号： H01L29/76

CPC分类号： H01L29/1054 ,  H01L21/02142 ,  H01L21/265 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834

摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

摘要翻译： 一种方法包括在半导体衬底上提供半导体合金层，在半导体合金层上形成栅极结构，在半导体衬底的栅极结构的两侧形成源区和漏极区，去除半导体合金层的至少一部分 覆盖源极和漏极区域，并且在源极和漏极区域上形成金属硅化物区域。

公开(公告)号：US08792078B2

公开(公告)日：2014-07-29

申请号：US12767152

申请日：2010-04-26

申请人： Cheng-Ming Lin ,  Chien-Chao Huang ,  Jong-Yuh Chang ,  Chia-Wei Chang ,  Boming Hsu

发明人： Cheng-Ming Lin ,  Chien-Chao Huang ,  Jong-Yuh Chang ,  Chia-Wei Chang ,  Boming Hsu

IPC分类号： G03B27/42

CPC分类号： G03F7/70983 ,  G03B27/58 ,  G03F1/64 ,  G03F7/70783

摘要： An apparatus for mounting a pellicle onto a mask is provided. In one embodiment, the apparatus comprises a base provided with a track; a dummy plate holder coupled to the base, the dummy plate holder for receiving a dummy plate having an elevated portion on one side thereof; a mask holder for receiving a mask, the mask holder slidably coupled to the base; a pellicle holder for receiving a pellicle frame, the pellicle holder slidably coupled to the base; and drive means being adapted to drive the pellicle holder along the track towards the dummy plate holder, wherein during operation when the pellicle frame is mounted onto the mask causing the mask to contact the dummy plate, the mounting pressure in the mask is distributed by way of the elevated portion in the dummy plate, thus reducing distortion in the mask.

摘要翻译： 提供了一种将防护薄膜组件安装在掩模上的装置。 在一个实施例中，该装置包括设置有轨道的基座; 耦合到基座的虚拟板保持器，用于接收在其一侧具有升高部分的虚拟板的虚拟板保持器; 用于接收掩模的掩模保持器，所述掩模保持器可滑动地联接到所述基部; 用于接收防护薄膜组件框架的防护薄膜组件保持器，所述防护薄膜组件保持器可滑动地联接到所述基座; 驱动装置适于将防护薄膜组件保持器沿着轨道朝向虚拟板夹持器驱动，其中在操作期间当防护薄膜组件框架安装在掩模上使得掩模与虚拟板接触时，掩模中的安装压力被分配 的虚拟板中的升高部分，从而减少掩模中的变形。

公开(公告)号：US20130045595A1

公开(公告)日：2013-02-21

申请号：US13210380

申请日：2011-08-16

申请人： Tsun-Min Cheng ,  Chien-Chao Huang ,  Chin-Fu Lin ,  Chi-Mao Hsu ,  Yen-Liang Lu ,  Chun-Ling Lin

发明人： Tsun-Min Cheng ,  Chien-Chao Huang ,  Chin-Fu Lin ,  Chi-Mao Hsu ,  Yen-Liang Lu ,  Chun-Ling Lin

IPC分类号： H01L21/283

CPC分类号： H01L21/76883

摘要： The method for processing a metal layer including the following steps is illustrated. First, a semiconductor substrate is provided. Then, a metal layer is formed over the semiconductor substrate. Furthermore, a microwave energy is used to selectively heat the metal layer without affecting the underlying semiconductor substrate and other formed structures, in which the microwave energy has a predetermined frequency in accordance with a material of the metal layer, and the predetermined frequency ranges between 1 KHz to 1 MHz.

摘要翻译： 示出了包括以下步骤的金属层的处理方法。 首先，提供半导体基板。 然后，在半导体衬底上形成金属层。 此外，使用微波能量来选择性地加热金属层，而不影响下面的半导体衬底和其它形成的结构，其中微波能量根据金属层的材料具有预定的频率，并且预定的频率范围在1 KHz至1MHz。

公开(公告)号：US20110298049A1

公开(公告)日：2011-12-08

申请号：US13210993

申请日：2011-08-16

申请人： Chun-Sheng Liang ,  Hung-Ming Chen ,  Chien-Chao Huang ,  Fu-Liang Yang

发明人： Chun-Sheng Liang ,  Hung-Ming Chen ,  Chien-Chao Huang ,  Fu-Liang Yang

IPC分类号： H01L27/092

CPC分类号： H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor. The NMOS device in the NMOS region includes a second gate stack on the semiconductor substrate; a second offset spacer on a sidewall of the second gate stack; a second raised source/drain extension region on the semiconductor substrate and adjoining the second offset spacer; and a deep source/drain region adjoining the second raised source/drain extension region, wherein the deep source/drain region is free from stressors formed in the semiconductor substrate.

摘要翻译： 半导体结构包括：包括PMOS区域和NMOS区域的半导体衬底; PMOS区域中的PMOS器件; 和NMOS区域中的NMOS器件。 PMOS器件包括在半导体衬底上的第一栅叠层; 在所述第一栅极堆叠的侧壁上的第一偏移间隔物; 所述半导体衬底中的应力源并且与所述第一偏移间隔物相邻; 以及在所述应力器上并与所述第一偏移间隔物邻接的第一升高的源极/漏极延伸区域，其中所述第一升高的源极/漏极延伸区域具有比所述应力源更高的p型掺杂剂浓度。 NMOS区域中的NMOS器件包括在半导体衬底上的第二栅极堆叠; 在所述第二栅极堆叠的侧壁上的第二偏移间隔物; 在所述半导体衬底上的第二凸起的源极/漏极延伸区域，并邻接所述第二偏移间隔物; 以及与第二升高源极/漏极延伸区域相邻的深源极/漏极区域，其中深的源极/漏极区域没有形成在半导体衬底中的应力源。

公开(公告)号：US07602006B2

公开(公告)日：2009-10-13

申请号：US11111282

申请日：2005-04-20

申请人： Chien-Chao Huang ,  Chi Min-Hwa ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Chi Min-Hwa ,  Fu-Liang Yang

IPC分类号： H01L29/94

CPC分类号： H01L29/7881 ,  H01L29/42324

摘要： A flash memory device includes a floating gate made of a multi-layered structure. The floating gate includes a hetero-pn junction which serves as a quantum well to store charge in the floating gate, thus increasing the efficiency of the device, allowing the device to be operable using lower voltages and increasing the miniaturization of the device. The floating gate may be used in n-type and p-type devices, including n-type and p-type fin-FET devices. The stored charge may be electrons or holes.

摘要翻译： 闪存器件包括由多层结构制成的浮动栅极。 浮置栅极包括用作在浮动栅极中存储电荷的量子阱的异质pn结，从而提高器件的效率，允许器件使用更低的电压可操作并且增加器件的小型化。 浮栅可用于n型和p型器件，包括n型和p型鳍式FET器件。 存储的电荷可以是电子或空穴。

公开(公告)号：US20090232384A1

公开(公告)日：2009-09-17

申请号：US12048043

申请日：2008-03-13

申请人： Chih-Chiang Tu ,  Chien-Chao Huang

发明人： Chih-Chiang Tu ,  Chien-Chao Huang

IPC分类号： G06K9/00

CPC分类号： G03F1/84

摘要： The present disclosure provide a method for making a mask. The method includes assigning a plurality of pattern features to different data types; writing the plurality of pattern features on a mask; inspecting the plurality of pattern features with different inspection sensitivities according to assigned data types; and repairing the plurality of pattern features on the mask according to the inspecting of the plurality of pattern features.

摘要翻译： 本公开提供了一种制造掩模的方法。 该方法包括将多个模式特征分配给不同的数据类型; 在掩模上写入多个图案特征; 根据分配的数据类型检查具有不同检查灵敏度的多个图案特征; 以及根据所述多个图案特征的检查来修复所述掩模上的所述多个图案特征。

公开(公告)号：US20090203202A1

公开(公告)日：2009-08-13

申请号：US12404050

申请日：2009-03-13

申请人： Chien-Chao Huang ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Fu-Liang Yang

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823842

摘要： Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode.

摘要翻译： 本发明的实施例提供一种半导体器件和制造方法。 制造MOS器件及其多晶或非晶栅电极，使得栅电极内的本征应力在MOS源/漏区之间的沟道区产生应力。 实施例包括在将中间NMOS栅极电极层的一部分转换成非晶层之后形成NMOS器件和PMOS器件，然后在图案化之前将其重结晶以形成电极。 NMOS再结晶栅电极中的平均晶粒尺寸小于PMOS再结晶栅电极中的平均晶粒尺寸。 在另一实施例中，NMOS器件包括非晶栅电极。