公开(公告)号：US20240120947A1

公开(公告)日：2024-04-11

申请号：US17961805

申请日：2022-10-07

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: H03M13/15 ,  H03M13/00 ,  H03M13/11

CPC classification number: H03M13/159 ,  H03M13/1105 ,  H03M13/611

Abstract: Methods, systems, and devices for error detection and classification at a host device are described. A host device may communicate a read command for a codeword stored at a memory device. In response to communicating the read command, the host device may receive the codeword and an error indication bit that indicates whether the memory device detected an error in the codeword. The host device may use the codeword to generate a set of syndrome bits. The host device may determine an error status of the codeword based on the error indication bit for the codeword and the set of syndrome bits for the codeword.

公开(公告)号：US20240118961A1

公开(公告)日：2024-04-11

申请号：US17938898

申请日：2022-10-07

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F11/07 ,  G06F11/10

CPC classification number: G06F11/0772 ,  G06F11/0793 ,  G06F11/1068

Abstract: Methods, systems, and devices for error detection and classification are described. A memory device may read a codeword from a memory and generate a first set of syndrome bits for the codeword. The memory device may use the first set of syndrome bits to generate a first error detection bit. The memory device may generate a second set of syndrome bits for the codeword and use the second set of syndrome bits to generate a second error detection bit. The memory device may provide the first error detection bit and the second error detection bit to a host device.

公开(公告)号：US20240103966A1

公开(公告)日：2024-03-28

申请号：US17934452

申请日：2022-09-22

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/0793

Abstract: Methods, systems, and devices for redundancy-based error detection in a memory device are described. A memory device may read multiple copies of a codeword from memory and generate for each codeword copy an error detection bit that indicates whether the memory device detected an error in that codeword. Additionally, the memory device may compare the codeword copies and generate one or more match bits that indicate whether corresponding portions of the codewords match. Using a combination of the error detection bits and the match bits, the memory device may determine the error status of each codeword.

公开(公告)号：US11928333B2

公开(公告)日：2024-03-12

申请号：US17946183

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F3/06 ,  G11C7/20 ,  G11C11/4072

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G11C7/20 ,  G11C11/4072

Abstract: Methods, systems, and devices for reset verification in a memory system are described. In some examples, a memory device may perform a reset operation and set a mode register to a first value based on performing the reset operation. The first value may be associated with a successful execution of the reset command. The memory device may transmit an indication to a host device based on determining the first value. The host device may determine from the received indication or from the first value stored in the mode register that the first value is associated with the successful execution of the reset command. Thus, the memory device, or the host device, or both may be configured to verify whether the reset operation is successful.

公开(公告)号：US11928018B2

公开(公告)日：2024-03-12

申请号：US17889203

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F11/1048

Abstract: Methods, systems, and devices for coordinated error protection are described. A set of data and an indication of whether a first management procedure performed by a memory device on the set of data detected one or more errors in the set of data may be received at a host device. At the host device, a second error management procedure may be performed on the set of data received from the memory device. Based on the received indication and the second error management procedure, multiple bits indicating whether one or more errors associated with the set of data were detected at the memory device, the host device, or both may be generated. The set of data may be validated or discarded based on the multiple bits.

公开(公告)号：US11829612B2

公开(公告)日：2023-11-28

申请号：US17396528

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Lance W Dover ,  Steffen Buch

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for security techniques for low power state of memory device are described. A host device may initiate a low power state of a memory device. The host device may store a first value of a counter associated with the memory device operating in the low power state and transmit a command to the memory device to enter the low power state. The memory device may increment the counter based on receiving the command and increment the counter to a second value. The host device may validate the memory device based on a difference between the first value of the counter stored by the host device and the second value of the counter.

公开(公告)号：US11711797B2

公开(公告)日：2023-07-25

申请号：US17891746

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo ,  Glen E. Hush ,  Aaron P. Boehm

IPC: H04W72/12 ,  H04W72/1263 ,  H04B1/38 ,  G06F9/30 ,  H04W72/23 ,  H04W92/18 ,  H04W84/04

CPC classification number: H04W72/1263 ,  G06F9/3001 ,  H04B1/38 ,  H04W72/23 ,  H04W84/042 ,  H04W92/18

Abstract: Systems, apparatuses and method related to remotely executable instructions are described. A device may be wirelessly coupled to (e.g., physically separated) another device, which may be in a physically separate device. The another device may remotely execute instructions associated with performing various operations, which would have been entirely executed at the device absent the another device. The outputs obtained as a result of the execution may be transmitted, via the transceiver, back to the device via a wireless communication link (e.g., using resources of an ultra high frequency (UHF), super high frequency (SHF), extremely high frequency (EHF), and/or tremendously high frequency (THF) bands). The another device at which the instructions are remotely executable may include memory resources, processing resources, and transceiver resources; they may be configured to use one or several communication protocols over licensed or shared frequency spectrum bands, directly (e.g., device-to-device) or indirectly (e.g., via a base station).

公开(公告)号：US11709715B2

公开(公告)日：2023-07-25

申请号：US17943148

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Glen E. Hush ,  Fa-Long Luo

IPC: G06F9/50 ,  G06F12/02 ,  G06F12/14

CPC classification number: G06F9/5061 ,  G06F12/023 ,  G06F12/1425 ,  G06F2212/1016 ,  G06F2212/1052

Abstract: Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.

公开(公告)号：US20230141845A1

公开(公告)日：2023-05-11

申请号：US18093762

申请日：2023-01-05

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Todd Jackson Plum ,  Mark D. Ingram ,  Scott E. Schaefer ,  Scott D. Van De Graaff

IPC: G06F12/02 ,  G06F11/34

CPC classification number: G06F12/023 ,  G06F11/3495 ,  G06F2212/7211

Abstract: Methods, systems, and devices for adaptive user defined health indications are described. A host device may be configured to dynamically indicate adaptive health flags for monitoring health and wear information for a memory device. The host device may indicate, to a memory device, a first index. The first index may correspond to a first level of wear of a set of multiple indexed levels of wear for the memory device. The memory device may determine that a metric of the memory device satisfies the first level of wear and indicate, to the host device, that the first level of wear is satisfied. The host device may receive the indication that the first level of wear is satisfied and indicate, to the memory device, a second level of wear of the set of indexed levels of wear that is different than the first level of wear.

公开(公告)号：US20230028176A1

公开(公告)日：2023-01-26

申请号：US17956551

申请日：2022-09-29

Applicant: Micron Technology, Inc.

Inventor： Debra M Bell ,  Kristen M. Hopper ,  Erika Prosser ,  Aaron P. Boehm

IPC: G06F11/07 ,  G06F3/06 ,  G06F1/30 ,  G06F1/20 ,  G06F11/30

Abstract: Methods, systems, and devices for persistent health monitoring for volatile memory devices are described. A memory device may determine that an operating condition associated with an array of memory cells on the device, such as a temperature, current, voltage, or other metric of health status is outside of a range associated with a risk of device degradation. The memory device may monitor a duration over which the operating condition is outside of the range, and may determine whether the duration satisfies a threshold. In some cases, the memory device may store an indication of when (e.g., each time) the duration satisfied the threshold. The memory device may store the one or more indications in one or more non-volatile storage elements, such as fuses, which may enable the memory device to maintain a persistent indication of a cumulative duration over which the memory device is operated with operating conditions outside of the range.