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公开(公告)号：US11216349B2
公开(公告)日：2022-01-04
申请号：US16159132
申请日：2018-10-12
发明人： Harish Reddy Singidi , Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla , Jianmin Huang , Xiangang Luo , Ashutosh Malshe
摘要： A variety of applications can include apparatus and/or methods to preemptively detect detect one memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facilitate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US20210350871A1
公开(公告)日：2021-11-11
申请号：US17382926
申请日：2021-07-22
发明人： Jianmin Huang , Deping He , Xiangang Luo , Harish Reddy Singidi , Kulachet Tanpairoj , Xu Zhang , Ting Luo
摘要： Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.
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公开(公告)号：US10977115B2
公开(公告)日：2021-04-13
申请号：US16159027
申请日：2018-10-12
发明人： Harish Reddy Singidi , Xiangang Luo , Jianmin Huang , Kishore Kumar Muchherla , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Sampath Ratnam
IPC分类号： G06F11/10 , G11C7/10 , G11C11/419 , G06F12/02
摘要： Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.
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公开(公告)号：US20210098030A1
公开(公告)日：2021-04-01
申请号：US17122531
申请日：2020-12-15
发明人： Xiangang Luo , Jianmin Huang , Patroclo Fumagalli , Scott Anthony Stoller , Alessandro Magnavacca , Andrea Pozzato
IPC分类号： G11C5/14 , G06F11/07 , G11C29/38 , G11C11/4099
摘要： Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of zeros in the first physical page.
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公开(公告)号：US20210042181A1
公开(公告)日：2021-02-11
申请号：US16533328
申请日：2019-08-06
发明人： Vamsi Pavan Rayaprolu , Harish R. Singidi , Kishore Kumar Muchherla , Ashutosh Malshe , Xiangang Luo
IPC分类号： G06F11/07
摘要： A memory access operation can be determined to have failed. A determination can be made as to whether a performance of a first error control operation has remedied the failure of the memory access operation. In response to determining that the first error control operation has remedied the failure of the memory access operation, an order of a performance of one or more prioritized error control operations of the plurality of prioritized error control operations can be changed for a subsequent memory access operation that has failed based on the first error control operation that has remedied the failure.
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公开(公告)号：US20210011767A1
公开(公告)日：2021-01-14
申请号：US16510526
申请日：2019-07-12
发明人： Xiangang Luo , Jianmin Huang
摘要： Apparatus and methods are disclosed, including using a memory controller to track a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data. A portion of a pool of memory cells of the memory device is reallocated from single level cell (SLC) static cache to SLC dynamic cache storage based at least in part on a value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register, in some examples.
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公开(公告)号：US20200212935A1
公开(公告)日：2020-07-02
申请号：US16235171
申请日：2018-12-28
发明人： Xiangang Luo , Ting Luo
摘要： Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum.
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公开(公告)号：US10446237B1
公开(公告)日：2019-10-15
申请号：US16024316
申请日：2018-06-29
发明人： Xiangang Luo , Jianmin Huang , Jung Sheng Hoei , Harish Reddy Singidi , Ting Luo , Ankit Vashi
摘要： Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level.
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公开(公告)号：US11579996B2
公开(公告)日：2023-02-14
申请号：US17692777
申请日：2022-03-11
发明人： Jianmin Huang , Xiangang Luo , Kulachet Tanpairoj
摘要： A memory device comprises a memory control unit including a processor configured to control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption; monitor operating conditions of the memory array for the P/E cycles, error management operations, DWPD, and power consumption; determine when a boundary condition for one of the multiple operating conditions is met; and in response to determining that a first boundary condition for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a change boundary condition of a second monitored operating condition.
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公开(公告)号：US20220300186A1
公开(公告)日：2022-09-22
申请号：US17203474
申请日：2021-03-16
发明人： Kishore Kumar Muchherla , Devin M. Batutis , Xiangang Luo , Mustafa N. Kaynak , Peter Feeley , Sivagnanam Parthasarathy , Sampath Ratnam , Shane Nowell
IPC分类号： G06F3/06
摘要： A current memory access voltage distribution is measured for a memory page of a block family associated with a first voltage bin of a plurality of voltage bins at a memory device. The first voltage bin is associated with a first voltage offset. A current value for a reference voltage is determined based on the current memory access voltage distribution measured for the memory page. An amount of voltage shift for the memory page is determined based on the current value for the reference voltage a prior value for the reference voltage. The prior value for the reference voltage is associated with a prior memory access voltage distribution for the memory page. In response to a determination that the amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the plurality of voltage bins. The second voltage bin is associated with a second voltage offset.
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